- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295335 > CS2200-CP-CZZR (CIRRUS LOGIC INC) PHASE LOCKED LOOP, 75 MHz, PDSO10 PDF資料下載
參數(shù)資料
| 型號(hào)： | CS2200-CP-CZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, 75 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁(yè)數(shù)： | 6/26頁(yè) |
| 文件大?。?/td> | 307K |
| 代理商： | CS2200-CP-CZZR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)
CS2200-CP
14
DS759PP1
5.3
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.
The driver can be set to high-impedance with the ClkOutDis bit.
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state
CLK_OUT may then be unreliable during an unlock condition.
Figure 8. PLL Clock Output Options
5.4
Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 9, to one of three signals: refer-
ence clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is con-
trolled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control
the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22). If AUX_OUT is set to
CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The
driver for the pin can be set to high-impedance using the AuxOutDis bit.
Figure 9. Auxiliary Output Selection
Referenced Control
Register Location
ClkOutUnl.............................. “Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
ClkOutDis .............................. “PLL Clock Output Disable (ClkOutDis)” on page 20
Referenced Control
Register Location
AuxOutSrc[1:0]...................... “Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 20
AuxOutDis .............................“Auxiliary Output Disable (AuxOutDis)” on page 19
AuxLockCfg........................... “AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 22
PLL Locked/Unlocked
PLL Output
2:1 Mux
ClkOutDis
2:1 Mux
ClkOutUnl
0
PLL Clock Output Pin
(CLK_OUT)
0
1
0
1
PLL Clock Output
PLLClkOut
3:1 Mux
Auxiliary Output Pin
(AUX_OUT)
AuxOutDis
AuxOutSrc[1:0]
AuxLockCfg
Timing Reference Clock
(RefClk)
PLL Clock Output
(PLLClkOut)
PLL Lock/Unlock Indication
(Lock)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS235GDWR18 | SPECIALTY ANALOG CIRCUIT, PDSO18 |
| CS3717AGNF16 | STEPPER MOTOR CONTROLLER, 1 A, PDIP16 |
| CS3972YDW16 | 3 A SWITCHING CONTROLLER, 47 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5157GD16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5165GDWR16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS2200CP-CZZR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZ | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。