參數(shù)資料
型號(hào): CS2200-CP-CZZR
廠商: CIRRUS LOGIC INC
元件分類: XO, clock
英文描述: PHASE LOCKED LOOP, 75 MHz, PDSO10
封裝: 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁數(shù): 21/26頁
文件大?。?/td> 307K
代理商: CS2200-CP-CZZR
CS2200-CP
4
DS759PP1
1. PIN DESCRIPTION
Pin Name
#
Pin Description
VD
1
Digital Power (Input) - Positive power supply for the digital and analog sections.
GND
2
Ground (Input) - Ground reference.
CLK_OUT
3
PLL Clock Output (Output) - PLL clock output.
AUX_OUT
4
Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks,
or a status signal, depending on register configuration.
TST_IN
5
Test Input (Input) - This pin is for factory test purposes and must be connected to GND for proper
operation.
XTO
XTI/REF_CLK
6
7
Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) -
XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input
clock. REF_CLK is an input for an externally generated low-jitter reference clock.
AD0/CS
8
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC
Mode. CS is the chip select signal in SPI Mode.
SCL/CCLK
9
Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in IC and SPI
mode.
SDA/CDIN
10
Serial Control Data (Input/Output) - SDA is the data I/O line in IC Mode. CDIN is the input data
line for the control port interface in SPI Mode.
1
2
3
4
5
6
7
8
9
10
XTO
CLK_OUT
GND
VD
XTI/REF_CLK
AD0/CS
SCL/CCLK
SDA/CDIN
AUX_OUT
TST_IN
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