- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295335 > CS2200-CP-CZZR (CIRRUS LOGIC INC) PHASE LOCKED LOOP, 75 MHz, PDSO10 PDF資料下載
參數(shù)資料
| 型號： | CS2200-CP-CZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, 75 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 307K |
| 代理商： | CS2200-CP-CZZR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁
CS2200-CP
22
DS759PP1
8.6
Function Configuration 1 (Address 16h)
8.6.1
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note:
AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.2
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
8.7
Function Configuration 2 (Address 17h)
8.7.1
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
76543210
Reserved
AuxLockCfg
Reserved
RefClkDiv1
RefClkDiv0
Reserved
AuxLockCfg
AUX_OUT Driver Configuration
0
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application:
RefClkDiv[1:0]
Reference Clock Input Divider
REF_CLK Frequency Range
00
÷4.
32 MHz to 75 MHz (50 MHz with XTI)
01
÷ 2.
16 MHz to 37.5 MHz
10
÷ 1.
8 MHz to 18.75 MHz
11
Reserved.
Application:
76543210
Reserved
ClkOutUnl
Reserved
ClkOutUnl
Clock Output Enable Status
0
Clock outputs are driven ‘low’ when PLL is unlocked.
1
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS235GDWR18 | SPECIALTY ANALOG CIRCUIT, PDSO18 |
| CS3717AGNF16 | STEPPER MOTOR CONTROLLER, 1 A, PDIP16 |
| CS3972YDW16 | 3 A SWITCHING CONTROLLER, 47 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5157GD16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| CS5165GDWR16 | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS2200CP-CZZR | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZ | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200CP-DZZR | 功能描述:時鐘合成器/抖動清除器 IC General Purpose PLL Crystal RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CS2200-OTP | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
| CS2200-OTP_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Fractional-N Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。