- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10681 > CS5529-ASZ (Cirrus Logic Inc)IC ADC 16BIT W/6BIT LATCH 20SSOP PDF資料下載
參數(shù)資料
| 型號： | CS5529-ASZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/31頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1015-ND - EVAL BOARD FOR CS5529 |
| 其它名稱： | 598-1110-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
CS5529
22
DS246F5
SDO flag falls. For instance, the user can just read
the conversion data register again to exit the contin-
uous conversion mode.
Note:
1) If the user begins to clear the SDO flag and
read the conversion data, this action must be
finished before the conversion cycle which is
occurring in the background is complete if the
user wants to be able to read the new
conversion data.
2) If a CC command is issued to the converter
while it is performing a conversion, the filter
will stop the current conversion and start a
new convolution cycle to perform a new
conversion.
3) Continuous conversions aren’t allowed
unless the port flag bit is set in the
configuration register.
4) The converter will remain in data mode and
continually perform conversions until the exit
command is issued (i.e. to exit the user must
read a register).
Output Coding
As shown in the Output Conversion Data Register
Descriptions, the CS5529 presents output conver-
sions as a 24-bit conversion word. The first 16 bits
of the conversion word represent conversion data.
The third byte contains two error flag bits.
In the third byte, D7-D4 are always logic 1; D3-D2
are always logic 0; and bits D1-D0 are the two flag
bits. The OF (Overrange Flag) bit is set to a logic 1
any time the input signal is: 1) more positive than
positive full scale, 2) more negative than zero (un-
ipolar mode), 3) more negative than negative full
scale (bipolar mode). It is cleared back to logic 0
whenever a conversion word occurs which is not
overranged.The OD (Oscillation Detect) bit is set to
a logic 1 any time that an oscillatory condition is de-
tected in the modulator. This does not occur under
normal operating conditions, but may occur when-
ever the input to the converter is extremely over-
ranged. If the OD bit is set, the conversion data bits
can be completely erroneous. The OD flag bit will be
cleared to logic 0 when the modulator becomes sta-
ble.
Table 2 and Table 3 illustrate the output coding for
the CS5529. Unipolar conversions are output in bi-
nary format and bipolar conversions are output
two's complement.
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
MSB
141312
11
10
9
8
7
6
5
4
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3
2
1
LSB
1
0
OD
OF
Table 2. Output Conversion Data Register Description (16 bits + flags).
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges,
or the voltage between
± full scale for any of the bipolar gain ranges. See text about error flags under
overrange conditions.
Unipolar Input Voltage
Offset Binary
Bipolar Input Voltage
Two's
Complement
>(VFS-1.5 LSB)
FFFF
>(VFS-1.5 LSB)
7FFF
VFS-1.5 LSB
FFFF
-----
FFFE
VFS-1.5 LSB
7FFF
-----
7FFE
VFS/2-0.5 LSB
8000
-----
7FFF
-0.5 LSB
0000
-----
FFFF
+0.5 LSB
0001
-----
0000
-VFS+0.5 LSB
8001
-----
8000
<(+0.5 LSB)
0000
<(-VFS+0.5 LSB)
8000
Table 3. CS5529 16-bit Output Coding.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-22Z-MW-B1 | CONVERTER MOD DC/DC 2V 40W |
| AD7798BRUZ | IC ADC 16BIT SIG-DEL 3CH 16TSSOP |
| VI-22T-MY-B1 | CONVERTER MOD DC/DC 6.5V 50W |
| AD9281ARSZ | IC ADC 8BIT DUAL CMOS 28-SSOP |
| AD8564ARZ-REEL7 | IC COMPARATOR QUAD 7NS 16SOIC TR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5529-ASZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC Prgrmbl Dlt Sigma ADC w/6-Bit Latch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5530 | 制造商:Texas Instruments 功能描述: |
| CS5530_0911 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-bit ADC with Ultra-low-noise Amplifier |
| CS5530A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
| CS5530A-UCE | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。