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參數(shù)資料
| 型號(hào)： | CS5529-ASZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 2/31頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1015-ND - EVAL BOARD FOR CS5529 |
| 其它名稱： | 598-1110-5 |
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CS5529
10
DS246F5
GENERAL DESCRIPTION
The CS5529 is a 16-bit
Σ Analog-to-Digital Con-
verter (ADC) which includes coarse/fine charge
buffers, a fourth order
Σ modulator, a calibration
microcontroller, eight digital filters which provide
selectable decimation rates, a 6-bit output latch,
and a three-wire serial interface. The ADC is opti-
mized to digitize unipolar or bipolar signals in in-
dustrial applications.
The digital filters provide eight selectable output
word rates (OWRs) of 1.88 Sps, 3.76 Sps, 7.51 Sps,
15.0 Sps, 30.0 Sps, 61.6 Sps, 84.5 Sps, 101.1 Sps
when operated from a 32.768 kHz watch crystal or
equivalent clock (output word rates can be in-
creased by approximately 3X by using 100 kHz
clock). The filters are designed to settle to full ac-
curacy for the selected output word rate in one con-
version. When operated at word rates of 15 Sps or
less (XIN = 32.768 kHz), the filter rejects both 50
Hz and 60 Hz line interference simultaneously.
Analog Input
The CS5529 provides a nominal 2.5 V input span
when the gain register is 1.0 decimal and the differ-
ential reference voltage between VREF+ and
VREF- is 2.5 V. The gain registers content is used
during calibration to set the gain slope of the
ADC’s transfer function. The differential reference
voltage magnitude and the gain register are two
factors that can be used to scale the nominal 2.5 V
input span. After reset, the gain register defaults to
1.0 decimal. In this case, the external voltage be-
tween the VREF+ pin and the VREF- pin sets the
ADC’s nominal full scale input span to 2.5 V. If a
user want to modify the input span, either the gain
register or the reference voltage’s magnitude needs
to be changed. For example, if a 1.25 V reference is
used in place of the nominal 2.5 V input, the full-
scale span is cut in half. To achieve the same 1.25V
input span, the user could simply use a 2.5 V refer-
ence and modify the gain register to 2.0 decimal.
Note that to keep from saturating the analog front
end, the input span must stay at or below 1.5 times
the reference voltage. This corresponds to a gain
register of 0.666... when a 2.5 V reference voltage
is used.
Note:
When a smaller reference voltage is used,
the resulting code widths are smaller. Since
the output codes exhibit more changing
codes for a fixed amount of noise, the
converter appears noisier.
Calibration can also affect the ADC’s full scale
span because system gain calibration can be used to
increase or decrease the full scale span of the
ADC’s transfer functions. At its limit, the input full
scale can be reduced to the point in which the gain
register reaches its upper limit of 3.999... (this will
occur when the ADC is gain calibrated with an in-
put signal less than or equal to approximately 1/4 of
its nominal full scale, if the ADC does not have in-
trinsic gain error). Calibration and its effects on the
analog input span is detailed in a later section of the
data sheet.
Analog Input Model
Figure 1 illustrates the input models for the AIN
pins. The model includes a coarse/fine charge buff-
er which reduces the dynamic current demands
from the signal source. The buffer is designed to
accommodate rail to rail (common-mode plus sig-
nal) input voltages. Typical CVF (sampling) cur-
rent is about 16nA (XIN = 32.768 kHz, see Figure
1). Application Note 30, “Switched-Capacitor A/D
Input Structures”, details various input architec-
tures.
Voltage Reference Input Model
Figure 2 illustrates the input models for the VREF
pins. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-
nal reference. Typical CVF (sampling) current is
about 8nA (XIN = 32.768 kHz, see Figure 2).
The reference’s buffer is designed to accommodate
rail-to-rail (common-mode plus signal) input volt-
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參數(shù)描述 |
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| CS5529-ASZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC Prgrmbl Dlt Sigma ADC w/6-Bit Latch RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5530 | 制造商:Texas Instruments 功能描述: |
| CS5530_0911 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-bit ADC with Ultra-low-noise Amplifier |
| CS5530A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
| CS5530A-UCE | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
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