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參數(shù)資料
| 型號： | CSR2930800BA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FLASH MEMORY CMOS 8M (1M x 8/512K x 16) BIT |
| 中文描述： | 閃存的CMOS 800萬（100萬x 8/512K × 16）位 |
| 文件頁數(shù)： | 14/50頁 |
| 文件大?。?/td> | 475K |
| 代理商： | CSR2930800BA |
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CSR2930800BA
-90
14
I
FUNCTIONAL DESCRIPTION
1.
Read Mode
The CSR2930800BA have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least t
ACC
-t
OE
time.) When reading out a data without changing addresses
after power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”
2.
Standby Mode
There are two ways to implement the standby mode on the CSR2930800BA devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at V
CC
± 0.3
V. Under this condition the current consumed is less than 5
μ
A. The device can be read with standard access
time (t
CE
) from either of these standby modes. During Embedded Algorithm operation, V
CC
active current (I
CC2
)
is required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V
SS
± 0.3 V
(CE = “H” or “L”). Under this condition the current is consumed is less than 5
μ
A. Once the RESET pin is taken
high, the device requires t
RH
of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
3.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
CSR2930800BA data. This mode can be used effectively with an application requested low power consumption
such as handy terminals.
To activate this mode, CSR2930800BA automatically switch themselves to low power mode when
CSR2930800BA addresses remain stably during access fine of 150 ns. It is not necessary to control CE, WE,
and OE on the mode. Under the mode, the current consumed is typically 1
μ
A (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and CSR2930800BA read-out the data for changed addresses.
4.
Output Disable
With the OE input at a logic high level (V
IH
), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
5.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force V
ID
(11.5 V to 12.5 V) on address pin A
9
. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A
0
from V
IL
to V
IH
. All
addresses are DON’T CARES except A
0
, A
1
, A
6
, and A
-1
. (See “CSR2930800BA Sector Protection Verify
Autoselect Codes Table” in
I
DEVICE BUS OPERATION.)
The manufacturer and device codes may also be read via the command register, for instances when the
CSR2930800BA are erased or programmed in a system without access to high voltage on the A
9
pin. The
command sequence is illustrated in “CSR2930800BA Standard Command Definitions Table” (
I
DEVICE BUS
OPERATION). (Refer to “2. Autoselect Command” in
I
COMMAND DEFINITIONS.)
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