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參數(shù)資料
| 型號： | CSR2930800BA |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FLASH MEMORY CMOS 8M (1M x 8/512K x 16) BIT |
| 中文描述： | 閃存的CMOS 800萬（100萬x 8/512K × 16）位 |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 475K |
| 代理商： | CSR2930800BA |
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CSR2930800BA
-90
18
3.
Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle
operation. There are two “unlock” write cycles. These are followed by the program set-up command and data
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the
system at this particular instance of time. Hence, Data Polling must be performed at the memory location which
is being programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“1. Embedded Program
TM
Algorithm” in
I
FLOW CHART illustrates the Embedded Program
TM
Algorithm using
typical command strings and bus operations.
4.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See “8. Write Operation Status”.) at which time the device returns to read the mode.
Chip Erase Time; Sector Erase Time
×
All sectors + Chip Program Time (Preprogramming)
“2. Embedded Erase
TM
Algorithm” in
I
FLOW CHART illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
5.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of WE, while the command
(Data=30h) is latched on the rising edge of WE. After time-out of 50
μ
s from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on "CSR2930800BA
Standard Command Definitions Table" in
I
DEVICE BUS OPERATION. This sequence is followed with writes
of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 μs otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50
μ
s from the rising edge of
the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs
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