參數(shù)資料
型號(hào): CXD3500R
廠商: Sony Corporation
英文描述: Timing Generator for LCD Panel(LCD面板的定時(shí)信號(hào)發(fā)生器)
中文描述: 時(shí)序發(fā)生器的液晶面板(液晶面板的定時(shí)信號(hào)發(fā)生器)
文件頁數(shù): 24/73頁
文件大小: 792K
代理商: CXD3500R
– 24 –
CXD3500R
VPOL, HPOL
These bits are the data for switching the input vertical and horizontal sync signal polarity. Since signal
processing is performed with the sync signal polarity fixed to positive by the internal logic, the data must be
switched according to the polarity of the input sync signal.
Therefore, individually set VPOL and HPOL to H when the polarity of the input sync signal is positive, and to L
when the polarity is negative.
VSYNC may not be detected if the opposite polarity is set, so be sure to set the correct polarity.
HDNPOL
HDN (H return pulse) is the 1/N frequency divider output pulse for the PLL IC. The width of the HDN pulse is
calculated according to the setting of PLLP11 to 1 for the value of frequency division N, and that value is N/2.
HDNPOL is the data for setting the output polarity of this HDN pulse, and the relationship between its setting
and the pulse polarity is shown in the figure below.
HSYNC
HDN
N/2 clk
N clk
HDNPOL: H
HDNPOL: L
HPOL: L
ENB1, 2
Tclp
Wclp
CLP pulse center
CLP
CLPPOL
This bit sets the output polarity of pedestal clamp pulse CLP. When CLPPOL is H, the polarity of the CLP
pulse is positive, and when CLPPOL is L, the polarity of the CLP pulse is negative.
CLPW, CLPP
These bits set the CLP pulse output width and output phase. Both the width and the phase can be set to two
positions using 1 bit.
The CLP pulse center position is fixed regardless of the CLPW setting.
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
CLPW: L
32 clk
40 clk
50 clk
64 clk
80 clk
80 clk
86 clk
96 clk
CLPW: H
48 clk
60 clk
74 clk
96 clk
120 clk
120 clk
130 clk
144 clk
CLPP: L
48 clk
60 clk
77 clk
100 clk
124 clk
124 clk
133 clk
148 clk
CLPP: H
32 clk
40 clk
53 clk
68 clk
84 clk
84 clk
89 clk
100 clk
PLSSL2, 1, 0
Wclp
Tclp
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