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參數資料
| 型號： | CXD3500R |
| 廠商： | Sony Corporation |
| 英文描述： | Timing Generator for LCD Panel(LCD面板的定時信號發(fā)生器) |
| 中文描述： | 時序發(fā)生器的液晶面板（液晶面板的定時信號發(fā)生器） |
| 文件頁數： | 25/73頁 |
| 文件大?。?/td> | 792K |
| 代理商： | CXD3500R |
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CXD3500R
SLCNT
Setting via the external control pins can be selected by setting SLCNT to H.
The settings that can be made using the external pins are the right/left inversion discrimination settings RGT
and XRGT, and the setting for switching the LCD panel AC conversion signal FRP and XFRP pulse cycle.
SLFLD
This bit selects FLD (Pin 6) IN/OUT pin input and output. The CXD3500R performs field identification
internally. When SLFLD is L, the internally generated FLD pulse is selected and used for the internal circuit
logic.
The external FLD pulse is selected by setting SLFLD to H.
For normal data type signals, the field identification pulse FLD is inverted every vertical period. The polarity at
this time is not specified.
Note)
When inputting the FLD pulse from an external source, make sure that the FLD pulse transition point is
2H or more before the rising edge of VST.
SLRS
This bit switches the HSYNC edge-based 1/2 frequency divider reset on/off when generating the 1/2 clock
using the internal frequency divider.
When SLRS is H, reset is not applied; when SLRS is low, reset is applied every 1H.
There is no need to set this bit when inputting a 1/2 clock from an external source.
CKPOL
This bit performs the input clock polarity switching settings. CLK1 and 2 pass through this clock polarity
switching setting immediately after input. When CKPOL is L, the internal circuits operate according to the input
clock and the reverse polarity clock.
When setup and hold cannot be maintained because the phases of the HSYNC input and the master clock
input to the TG are offset due to the set system, set CKPOL to a value that provides sufficient margin.
SLCK
This bit switches the clock between the internal 1/2 frequency division and external 1/2 clock input.
When inputting an external 1/1 clock, set SLCK to H to 1/2 frequency divide the clock internally. When
inputting an external 1/2 clock, set SLCK to L.
When the master clock is 55MHz or more, input an external 1/2 frequency-divided clock and set SLCK to L.
Note)
Pulses with positions that can be set in 1-dot units (HST, HCK1, HCK2, ENB1, ENB2, PCG, PRG, CLP,
BLK, VCK transition point, FRP transition point and XFRP transition point) use the internally inverted
clock, so when inputting a 1/2 clock using an external frequency divider, these pulses may be offset if
the 1/2 clock duty deviates from 50%. Therefore, set the duty of the input 1/2 clock as close to 50% as
possible.
SLCNT: L
Address: 0C Data 4 RGT
Address: 07 Data 4 FRP0
SLCNT: H
External pin RGTCNT (Pin 10)
External pin FRPCNT (Pin 11)
相關PDF資料 |
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|---|---|
| CXD3503R | Color Shading Correction IC for Liquid Crystal Projectors |
| CXD3504R | Selective Delay Line For LCD(用于LCD的可選擇延遲線) |
| CXD3508ATQ | LCD Interface IC |
| CXD3508BTQ | LCD Interface IC |
| CXD3508TQ | LCD Interface IC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CXD3503R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Color Shading Correction IC for Liquid Crystal Projectors |
| CXD3504R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Color Shading Correction IC for Liquid Crystal Projectors |
| CXD3508ATQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
| CXD3508BTQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
| CXD3508TQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:LCD Interface IC |
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