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參數(shù)資料
| 型號： | CY28548ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 960M/965M 64TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時鐘 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:22 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
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CY28548
........................Document #: 001-08400 Rev ** Page 7 of 30
32
SRCC11/ CR#_G
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_G
Input Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
33
SRCT11/ CR#_H
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_H Input Selected
via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
34
SRCT10
O, DIF True 100 MHz differential serial reference clocks.
35
SRCC10
O, DIF Complementary 100 MHz differential serial reference clocks.
36
VDD_SRC_IO
PWR
3.3V-1.25V Power supply for outputs.
37
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
38
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
SRCC6
O, DIF Complementary 100 MHz differential serial reference clocks.
41
SRCT6
O, DIF True 100 MHz differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
43
SRCC7/ CR#_E
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input. Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
44
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_FInput.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
45
VDD_SRC_IO
PWR
3.3V-1.25V power supply for outputs.
46
SRCC8 / CPUC2_ITP
O, DIF Selectable Complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
47
SRCC8 / CPUC2_ITP
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
48
NC
No connect.
49
VDD_CPU_IO
PWR
3.3V-1.25V Power supply for outputs.
50
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
51
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
52
VSS_CPU
GND
Ground for outputs.
53
CPUC0
O, DIF Complementary differential CPU clock outputs.
54
CPUT0
O, DIF True differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
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