參數(shù)資料
型號： CY39100V388B-125MGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 10 ns, PBGA388
封裝： 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-388
文件頁數(shù)： 11/86頁
文件大?。?/td> 2677K
代理商： CY39100V388B-125MGXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 19 of 86
tCKIN
Delay from the clock pin to the input of the clock driver
tIOREGPIN
Delay from the I/O pin to the input of the I/O register
PLL Parameters
tMCCJ
Maximum cycle to cycle jitter time
tDWSA
PLL zero phase delay with clock tree deskewed
tDWOSA
PLL zero phase delay without clock tree deskewed
tLOCK
Lock time for the PLL
tINDUTY
Input duty cycle
fPLLI
Input frequency of the PLL
fPLLO
Output frequency of the PLL
fPLLVCO
PLL VCO frequency of operation
PSAPLLI
Percentage modulation allowed (spread awareness) on the PLL input clock
fMPLLI
Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI*
(1–PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100)
JTAG Parameters
tJCKH
TCLK HIGH time
tJCKL
TCLK LOW time
tJCP
TCLK clock period
tJSU
JTAG port set-up time (TDI/TMS inputs)
tJH
JTAG port hold time (TDI/TMS inputs)
tJCO
JTAG port clock to output time (TDO)
tJXZ
JTAG port valid output to high impedance (TDO)
tJZX
JTAG port high impedance to valid output (TDO)
Switching Characteristics — Parameter Descriptions Over the Operating Range[13] (continued)
Parameter
Description
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
Cluster memory access time. Delay from address change to Read data out
tCLMPWE
Write Enable pulse width
tCLMSA
Address set-up to the beginning of Write Enable with both signals from the same I/O block
tCLMHA
Address hold after the end of Write Enable with both signals from the same I/O block
tCLMSD
Data set-up to the end of Write Enable
tCLMHD
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCLMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCLMDV1
Global clock to data valid on output pins for flow through data
tCLMDV2
Global clock to data valid on output pins for pipelined data
tCLMMACS1
Cluster memory input clock to macrocell clock in the same cluster
tCLMMACS2
Cluster memory output clock to macrocell clock in the same cluster
tMACCLMS1
Macrocell clock to cluster memory input clock in the same cluster
相關(guān)PDF資料
PDF描述
CY39100V388B-83MGXC LOADABLE PLD, 15 ns, PBGA388
CY39200V208-125NTXC LOADABLE PLD, 10 ns, PQFP208
CY39050V208-125NTXC LOADABLE PLD, 10 ns, PQFP208
CY39050V208-125NTXI LOADABLE PLD, 10 ns, PQFP208
CY39050V208-233NTXC LOADABLE PLD, 7.2 ns, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V388B-200MGC 制造商:Cypress Semiconductor 功能描述:
CY39100V388B-200MGXC 功能描述:IC CPLD 100K GATE 388-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY39100V388B-83MGC 制造商:Cypress Semiconductor 功能描述:
CY39100V388B-83MGXC 功能描述:IC CPLD 100K GATE 388-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY39100V484-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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