參數(shù)資料
型號： CY39100V388B-125MGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 10 ns, PBGA388
封裝： 35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-388
文件頁數(shù)： 2/86頁
文件大?。?/td> 2677K
代理商： CY39100V388B-125MGXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 10 of 86
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. Unlike global control signals, these OCC signal can
be driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
DQ
RES
E
G
lobal
I
/O
C
ont
ro
lS
ignal
s
O
utput
C
ont
ro
lC
hannel
O
C
G
lobal
C
lock
S
ignal
s
Slew
Rate
Control
C
I/O
From
Output PIM
To Routing
Channel
OE Mux
Register Input
Mux
Register Enable
Mux
Output Mux
Clock Mux
Clock
Polarity
Mux
Register Reset
Mux
Input
Mux
Bus
Hold
C
DQ
RES
C
Registered OE
Mux
C
3
C
3
C
2
3
C
Figure 8. Block Diagram of I/O Cell
Table 3.
I/O Standards
I/O
Standard
VREF (V)
VCCIO
Termination
Voltage (VTT)
Min.
Max.
LVTTL
N/A
3.3V
N/A
LVCMOS
3.3V
N/A
LVCMOS3
3.0V
N/A
LVCMOS2
2.5V
N/A
LVCMOS18
1.8V
N/A
3.3V PCI
3.3V
N/A
GTL+
0.9
1.1
N/A
1.5
SSTL3 I
1.3
1.7
3.3V
1.5
SSTL3 II
1.3
1.7
3.3V
1.5
SSTL2 I
1.15
1.35
2.5V
1.25
SSTL2 II
1.15
1.35
2.5V
1.25
HSTL I
0.68
0.9
1.5V
0.75
HSTL II
0.68
0.9
1.5V
0.75
HSTL III
0.68
0.9
1.5V
1.5
HSTL IV
0.68
0.9
1.5V
1.5
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V388B-200MGC 制造商:Cypress Semiconductor 功能描述:
CY39100V388B-200MGXC 功能描述:IC CPLD 100K GATE 388-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY39100V388B-83MGC 制造商:Cypress Semiconductor 功能描述:
CY39100V388B-83MGXC 功能描述:IC CPLD 100K GATE 388-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Delta 39K™ ISR™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤
CY39100V484-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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