參數(shù)資料
型號: CY7C006A-15AI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 16K X 8 DUAL-PORT SRAM, 15 ns, PQFP64
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64
文件頁數(shù): 1/20頁
文件大?。?/td> 1051K
代理商: CY7C006A-15AI
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-06045 Rev. *B
Revised June 23, 2004
Features
True dual-ported memory cells which allow
simultaneous access of the same memory location
16K x 8 organization (CY7C006A)
32K x 8 organization (CY7C007A)
16K x 9 organization (CY7C016A)
32K x 9 organization (CY7C017A)
0.35-micron CMOS for optimum speed/power
High-speed access: 12[1]/15/20 ns
Low operating power
— Active: ICC = 180 mA (typical)
— Standby: ISB3 = 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flags for port-to-port communication
Pin select for Master or Slave
Commercial temperature range
Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1.
See page 7 for Load Conditions.
2.
I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3.
BUSY is an output in master mode and an input in slave mode.
4.
A0–A13 for 16K; A0–A14 for 32K devices.
I/O
Control
Address
Decode
A0L–A13/14L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
Logic Block Diagram
A0L–A13/14L
True Dual-Ported
RAM Array
A0R–A13/14R
CER
OER
R/WR
BUSYR
SEMR
INTR
Address
Decode
A0R–A13/14R
R/WL
OEL
I/O0L–I/O7/8L
CEL
R/WR
OER
I/O0R–I/O7/8R
CER
14/15
8/9
14/15
8/9
14/15
CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
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CY7C018V-25AI 64K X 9 DUAL-PORT SRAM, 25 ns, PQFP100
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