- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298975 > CY7C1020CV33-10ZXCT (CYPRESS SEMICONDUCTOR CORP) 32K X 16 STANDARD SRAM, 10 ns, PDSO44 PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1020CV33-10ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 32K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| 封裝： | LEAD FREE, TSOP2-44 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 133K |
| 代理商： | CY7C1020CV33-10ZXCT |
512K (32K x 16) Static RAM
CY7C1020CV33
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05133 Rev. *D
Revised March 7, 2005
Features
Pin- and function-compatible with CY7C1020V33
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
High speed
—tAA = 10, 12, 15 ns
CMOS for optimum speed/power
Low active power
— 360 mW (max.)
Automatic power-down when deselected
Independent control of upper and lower bits
Available in 44-pin TSOP II
Functional Description
The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP
Type II package.
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
A14
A13
A12
NC
A3
OE
VSS
A5
I/O16
A2
CE
I/O3
I/O1
I/O2
BHE
NC
A1
A0
18
17
20
19
I/O4
27
28
25
26
22
21
23
24
NC
VSS
I/O7
I/O5
I/O6
I/O8
A6
A7
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A8
A9
A10
A11
32K × 16
RAM Array
I/O1–I/O8
ROW
DEC
O
DER
A7
A6
A5
A4
A3
A0
COLUMN DECODER
A
9
A
10
A
11
A
12
A
13
A
14
SENSE
AMPS
DATA IN DRIVERS
OE
A2
A1
I/O9–I/O16
CE
WE
BLE
BHE
A
8
A4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1328F-133AC | 256K X 18 CACHE SRAM, 4 ns, PQFP100 |
| CY7C1339B-133BGIT | 128K X 32 CACHE SRAM, 4 ns, PBGA119 |
| CY7C1339G-200AXCT | 128K X 32 CACHE SRAM, 2.8 ns, PQFP100 |
| CY7C1347D-250BGC | 128K X 36 CACHE SRAM, 2.4 ns, PBGA119 |
| CY7C1512JV18-267BZXC | 4M X 18 QDR SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1020CV33-12ZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II |
| CY7C1020CV33-12ZCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II T/R |
| CY7C1020CV33-15BAXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1020CV33-15ZC | 功能描述:IC SRAM 512KBIT 15NS 44TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1020CV33-15ZCT | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。