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參數(shù)資料
| 型號(hào)： | CY7C006A-15AI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K X 8 DUAL-PORT SRAM, 15 ns, PQFP64 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 1051K |
| 代理商： | CY7C006A-15AI |
CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document #: 38-06045 Rev. *B
Page 5 of 20
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. The operation of the interrupts and their interaction
with Busy are summarized in Table 2.
Busy
The CY7C006A, CY7C007A, CY7C016A and CY7C017A pro-
vide on-chip arbitration to resolve simultaneous memory loca-
tion access (contention). If both ports’ CEs are asserted and an
address match occurs within tPS of each other, the busy logic will
determine which port has access. If tPS is violated, one port will defi-
nitely gain permission to the location, but it is not predictable which
port will get that permission. BUSY will be asserted tBLA after an ad-
dress match or tBLC after CE is taken LOW.
Master/Slave
A M/S pin is provided in order to expand the word width by configur-
ing the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (tBLC or tBLA), otherwise, the slave chip may begin a write
cycle during a contention situation. When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Semaphore Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A pro-
vide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For exam-
ple, if the left port wants to request a given resource, it sets a
latch by writing a zero to a semaphore location. The left port
then verifies its success in setting the latch by reading it. After
writing to the semaphore, SEM or OE must be deasserted for tSOP
before attempting to read the semaphore. The semaphore value will
be available tSWRD + tDOE after the rising edge of the semaphore
write. If the left port was successful (reads a zero), it assumes control
of the shared resource, otherwise (reads a one) it assumes the right
port has control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a one), the
left side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sample
semaphore operations.
When reading a semaphore, all data lines output the sema-
phore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the sema-
phore within tSPS of each other, the semaphore will definitely be
obtained by oneside or the other, but thereis noguarantee whichside
will control the semaphore.
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| CY7C006A-15AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5V 16Kx8 COM Dual Port 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C006A-15AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5V 16Kx8 COM Dual Port 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C006A-15JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 128K-Bit 16K x 8 15ns 68-Pin PLCC |
| CY7C006A-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| CY7C006A-20AC | 功能描述:IC SRAM 16KX8 DUAL 64LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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