參數(shù)資料
型號(hào)： CY7C025-35JC
英文描述： SRAM|8KX16|CMOS|LDCC|84PIN|PLASTIC
中文描述： 靜態(tài)存儲(chǔ)器| 8KX16 |的CMOS | LDCC | 84PIN |塑料
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 301K
代理商： CY7C025-35JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 8 of 20
Data Retention Mode
The CY7C0138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data reten-
tion:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Notes:
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
tWB
R/W HIGH after BUSY (Slave)
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
17
ns
tBDD
[22]
BUSY HIGH to Data Valid
20
25
ns
INTERRUPT TIMING[21]
tINS
INT Set Time
20
ns
tINR
INT Reset Time
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
ns
tSPS
SEM Flag Contention Window
5
ns
tSAA
SEM Address Access Time
20
25
ns
Switching Characteristics Over the Operating Range[15] (continued)
Parameter
Description
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Unit
-20
-25
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[23]
Max.
Unit
ICCDR1
@ VCCDR = 2V
50
A
Data Retention Mode
3.0V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
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CY7C025-35JI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
CY7C025-35JXC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
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