參數(shù)資料
型號: CY7C025-35JC
英文描述: SRAM|8KX16|CMOS|LDCC|84PIN|PLASTIC
中文描述: 靜態(tài)存儲器| 8KX16 |的CMOS | LDCC | 84PIN |塑料
文件頁數(shù): 20/20頁
文件大?。?/td> 301K
代理商: CY7C025-35JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 9 of 20
Switching Waveforms
Notes:
24. R/W is HIGH for read cycles.
25. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
26. OE = VIL.
27. Address valid prior to or coincident with CE transition LOW.
28. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
Read Cycle No. 1 (Either Port Address Access)[24, 25, 26]
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU
tPD
ISB
ICC
DATA OUT
OE
CE
CURRENT
Read Cycle No. 2 (Either Port CE/OE Access)[24, 27, 28]
DATA OUT
tRC
ADDRESS
tAA
tOHA
CE
tLZCE
tABE
tHZCE
tACE
tLZCE
Read Cycle No. 3 (Either Port)[24, 26, 27, 28]
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