參數(shù)資料
型號: CY7C025-35JC
英文描述: SRAM|8KX16|CMOS|LDCC|84PIN|PLASTIC
中文描述: 靜態(tài)存儲器| 8KX16 |的CMOS | LDCC | 84PIN |塑料
文件頁數(shù): 6/20頁
文件大?。?/td> 301K
代理商: CY7C025-35JC
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 14 of 20
Notes:
43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Switching Waveforms (continued)
Interrupt Timing Diagrams
WRITE FFF (See Functional Description)
tWC
Right Side Clears INT
R
:
tHA
READ FFF
tRC
tINR
WRITE FFE (See Functional Description)
tWC
Right Side Sets INTL:
Left Side Sets INT
R
:
Left Side Clears INT
L
:
READ FFE
tINR
tRC
ADDRESSR
CE L
R/W L
INT L
OE L
ADDRESSR
R/WR
CE R
INTL
ADDRESSR
CER
R/WR
INTR
OE R
ADDRESSL
R/W L
CE L
INTR
tINS
tHA
tINS
(See Functional Description)
[43]
[44]
[43]
[44]
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