參數(shù)資料
型號(hào): CY7C1021CV33-10ZIT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 64K X 16 STANDARD SRAM, 10 ns, PDSO44
封裝: TSOP2-44
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 554K
代理商: CY7C1021CV33-10ZIT
CY7C1021CV33
Document Number: 38-05132 Rev. *H
Page 3 of 14
Pin Definitions
Pin Name
SOJ, TSOP
Pin Number
BGA Pin
Number
IO Type
Description
A0–A15
1–5, 18–21,
24–27, 42–44
A3, A4, A5, B3,
B4, C3, C4,
D4, H2, H3,
H4, H5, G3,
G4, F3, F4
Input
Address Inputs. Used to select one of the address locations.
IO1–IO16 [2]
7–10, 13–16,
29–32, 35–38
B6, C6, C5,
D5, E5, F5, F6,
G6, B1, C1,
C2, D2, E2,
F2, F1, G1
Input or Output Bidirectional Data IO lines. Used as input or output lines depending
on operation.
NC
22, 23, 28
A6, D3, E3,
E4, G2, H1, H6
No Connect No Connects. Not connected to the die.
WE
17
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
6
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
40, 39
B2, A1
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls IO16 – IO9,
BLE controls IO8 – IO1.
OE
41
A2
Input or
Control
Output Enable, Active LOW. Controls the direction of the IO pins.
When LOW, the IO pins are allowed to behave as outputs. When
deasserted HIGH, the IO pins are tri-stated and act as input data
pins.
VSS
12, 34
D1, E6
Ground
Ground for the device. Connected to ground of the system.
VCC
11, 33
D6, E1
Power Supply Power Supply Inputs to the Device.
Note
2. IO1–IO16 for SOJ/TSOP and IO0–IO15 for BGA packages.
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