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| 型號(hào)： | CY7C109BL-15VI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K x 8 Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 546K |
| 代理商： | CY7C109BL-15VI |
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *B
Page 4 of 11
Switching Characteristics[5] Over the Operating Range
Parameter
Description
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
12
15
ns
tAA
Address to Data Valid
12
15
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data
Valid
12
15
ns
tDOE
OE LOW to Data Valid
6
7
ns
tLZOE
OE LOW to Low Z
0
ns
tHZOE
OE HIGH to High Z
[6, 7]
67
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[7]
33
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[6, 7]
67
ns
tPU
CE1 LOW to Power-Up, CE2 HIGH to
Power-Up
00
ns
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
12
15
ns
Write Cycle[8]
tWC
Write Cycle Time[9]
12
15
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
10
12
ns
tAW
Address Set-Up to Write End
10
12
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
10
12
ns
tSD
Data Set-Up to Write End
7
8
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[7]
33
ns
tHZWE
WE LOW to High Z[6, 7]
67
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C109BN-12VC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C109BN-12ZC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C109BN-12ZXC | 功能描述:IC SRAM 1MBIT 12NS 32TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C109BN-12ZXCT | 功能描述:IC SRAM 1MBIT 12NS 32TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C109BN-15VC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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