參數(shù)資料
型號(hào): CY7C109BL-15VI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): SRAM
英文描述: 128K x 8 Static RAM
中文描述: 128K X 8 STANDARD SRAM, 15 ns, PDSO32
封裝: 0.400 INCH, PLASTIC, SOJ-32
文件頁(yè)數(shù): 8/11頁(yè)
文件大?。?/td> 546K
代理商: CY7C109BL-15VI
CY7C109B
CY7C1009B
Document #: 38-05038 Rev. *B
Page 6 of 11
Switching Waveforms
Read Cycle No. 1[10, 11]
Read Cycle No. 2 (OE Controlled)[11, 12]
Write Cycle No. 1 (CE1 or CE2 Controlled)
[13, 14]
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
相關(guān)PDF資料
PDF描述
CY7C109BL-15ZC 128K x 8 Static RAM
CY7C1157V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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參數(shù)描述
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