參數(shù)資料
型號(hào): CY7C1177V18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)(2.5周期讀寫延遲)
文件頁(yè)數(shù): 14/27頁(yè)
文件大?。?/td> 963K
代理商: CY7C1177V18
CY7C1166V18
CY7C1177V18
CY7C1168V18
CY7C1170V18
Document Number: 001-06620 Rev. *C
Page 21 of 27
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
5pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
165 FBGA
Package
Unit
ΘJA
Thermal Resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
17.2
°C/W
ΘJC
Thermal Resistance
(junction to case)
4.15
°C/W
AC Test Loads and Waveforms
Figure 6. AC Test loads and Waveforms
1.25V
0.25V
R = 50
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
DEVICE
RL = 50
Z0 = 50
VREF = 0.75V
[19]
0.75V
UNDER
TEST
0.75V
DEVICE
UNDER
TEST
OUTPUT
0.75V
VREF
OUTPUT
ZQ
(a)
SLEW RATE= 2 V/ns
RQ =
250
(b)
RQ =
250
Notes
19. Unless otherwise noted, test conditions are based on a signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
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