- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295374 > CY7C1177V18 (Cypress Semiconductor Corp.) 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) PDF資料下載
參數(shù)資料
| 型號： | CY7C1177V18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)（2.5周期讀寫延遲） |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 963K |
| 代理商： | CY7C1177V18 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
CY7C1166V18
CY7C1177V18
CY7C1168V18
CY7C1170V18
Document Number: 001-06620 Rev. *C
Page 22 of 27
Switching Characteristics
Over the operating range[19, 20]
Cypress
Parameter
Consortium
Parameter
Description
400 MHz
375 MHz
333 MHz
300 MHz
Unit
Min Max Min Max Min Max Min Max
tPOWER
VDD(Typical) to the first Access[21]
1
–
1–
1–1–
ms
tCYC
tKHKH
K Clock Cycle Time
2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40
ns
tKH
tKHKL
Input Clock (K/K) HIGH
0.4–
0.4–0.4–0.4
–
tCYC
tKL
tKLKH
Input Clock (K/K) LOW
0.4
–
0.4
–
0.4
–
0.4
–
tCYC
tKHKH
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
–1.13–
1.28
–1.40–
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.4
–
0.4
–
ns
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
0.4
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
–0.28–
0.28
–0.28–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.4–
0.4–0.4–0.4
–
ns
tHC
tKHIX
Control Hold after K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
0.4
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS0, BWS1, BWS2, BWS3)
0.28
–0.28–
0.28
–0.28–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
tDOH
tCHQX
Data Output Hold after K/K Clock Rise
(Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tCCQO
tCHCQV
K/K Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
tCQOH
tCHCQX
Echo Clock Hold after K/K Clock Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
–
0.2
–
0.2
–
0.2
–
0.2
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.2
–
–0.2
–
–0.2
–
–0.2
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH[22]
0.81
–0.88–
1.03
–1.15–
ns
tCQHCQH tCQHCQH
CQ Clock Rise to CQ Clock Rise[22]
(rising edge to rising edge)
0.81
–0.88–
1.03
–1.15–
ns
tCHZ
tCHQZ
Clock (K/K) Rise to High-Z (Active to High-Z)[23, 24]
–0.45
–
0.45–
0.45
–0.45
ns
tCLZ
tCHQX1
Clock (K/K) Rise to Low-Z[23, 24]
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
tQVLD
Echo Clock High to QVLD Valid[25]
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
ns
DLL Timing
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
ns
tKC lock
DLL Lock Time (K)
2048
–
2048
–
2048
–
2048
–
Cycles
tKC Reset
K Static to DLL Reset[26]
30–30–30–30
–
ns
Notes
20. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
21. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
22. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.
23. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
24. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
25. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
26. Hold to >VIH or <VIL.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1215H-100AXC | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H-100AXI | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H-133AXC | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H-133AXI | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| CY7C1215H | 1-Mbit (32K x 32) Pipelined Sync SRAM |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。