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參數(shù)資料
| 型號(hào)： | CY7C1215H |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| 中文描述： | 1兆位（32K的× 32）流水線同步靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 361K |
| 代理商： | CY7C1215H |
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CY7C1215H
Document #: 38-05666 Rev. *B
Page 10 of 15
Switching Waveforms
Read Cycle Timing[16]
Note:
16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
tCYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
tAH
tAS
A1
tCEH
tCES
GW, BWE,
BW[A:D]
Data Out (Q)
High-Z
tCLZ
tDOH
tCO
ADV
tOEHZ
tCO
Single READ
BURST READ
tOEV
tOELZ
tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
Deselect
cycle
Burst continued with
new base address
DON’T CARE
UNDEFINED
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
| CY7C1218H-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1218H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1.125MBIT 32KX36 3.5NS 100TQFP - Bulk |
| CY7C1219F-133AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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