參數(shù)資料
型號: CY7C1215H
廠商: Cypress Semiconductor Corp.
英文描述: 1-Mbit (32K x 32) Pipelined Sync SRAM
中文描述: 1兆位(32K的× 32)流水線同步靜態(tài)存儲器
文件頁數(shù): 5/15頁
文件大?。?/td> 361K
代理商: CY7C1215H
CY7C1215H
Document #: 38-05666 Rev. *B
Page 13 of 15
ZZ Mode Timing[20, 21]
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in High-Z when exiting ZZ sleep mode.
Switching Waveforms (continued)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
[+] Feedback
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