參數(shù)資料
型號(hào)： CY7C1371AV25-66AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 1/26頁(yè)
文件大?。?/td> 333K
代理商： CY7C1371AV25-66AC
PRELIMINARY
512Kx36/1Mx18 Flow-Thru SRAM with NoBL Architecture
CY7C1371AV25
CY7C1373AV25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 6, 2000
25
Features
Pin compatible and functionally equivalent to ZBT
de-
vices
Supports 117-MHz bus operations with zero wait states
— Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
Registered inputs for Flow-Through operation
Byte Write capability
Common I/O architecture
Single 2.5V power supply
Fast clock-to-output times
— 7.5 ns (for 117-MHz device)
— 8.5 ns (for 100-MHz device)
— 9.0 ns (for 83-MHz device)
— 10.0 ns (for 66-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP & 119 BGA Packages
Burst Capability - linear or interleaved burst order
Functional Description
The CY7C1371AV25 and CY7C1373AV25 are 2.5V, 512K by
36 and 1M by 18 Synchronous-Flow-Through Burst SRAMs,
respectively designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1371AV25/CY7C1373AV25 is equipped
with the advanced No Bus Latency (NoBL
) logic required
to enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically im-
proves the throughput of data through the SRAM, especially in
systems that require frequent Write/Read transitions.The
CY7C1371AV25/CY7C1373AV25 is pin compatible and func-
tionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz de-
vice).
Write operations are controlled by the Byte Write Selects
(BWSa,b,c,d
for
CY7C1371AV25
and
BWSa,b
for
CY7C1373AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Synchronous Chip Enable (CE1, CE2, CE3 on the TQFP, CE1
on the BGA) and an asynchronous Output Enable (OE) pro-
vide for easy bank selection and output three-state control. In
order to avoid bus contention, the output drivers are synchro-
nously three-stated during the data portion of a write se-
quence.
.Introduction
CLK
Ax
CEN
WE
BWSx
CE1
CE
CE2
OE
256KX36/
MEMORY
ARRAY
Logic Block Diagram
DQx
Data-In REG.
Q
D
CE
CONTROL
and WRITE
LOGIC
3
ADV/LD
Mode
DPx
CY7C1371
CY7C1373
AX
DQX
DPX
BWSX
512KX18
X = 18:0
X = 19:0
X= a, b, c, d X = a, b
X = a, b
X = a, b, c, d
Selection Guide
117 MHz
100 MHz
83 MHz
66 MHz
Maximum Access Time (ns)
7.5
8.5
9.0
10.0
Maximum Operating Current (mA)
Com’l
250
230
215
180
Maximum CMOS Standby Current (mA)
30
Shaded areas contain advance information.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
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