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參數(shù)資料
| 型號： | CY7C1248KV18-400BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 907K |
| 代理商： | CY7C1248KV18-400BZXC |
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CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
36-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-57834 Rev. *B
Revised February 24, 2011
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■ 36 Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 450 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
[1]
Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 Cycles:
CY7C1246KV18 – 4 M × 8
CY7C1257KV18 – 4 M × 9
CY7C1248KV18 – 2 M × 18
CY7C1250KV18 – 1 M × 36
Functional Description
The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and
CY7C1250KV18 are 1.8 V synchronous pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1246KV18), 9-bit words (CY7C1257KV18), 18-bit
words (CY7C1248KV18), or 36-bit words (CY7C1250KV18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
450 MHz
400 MHz
375 MHz
333 MHz
Unit
Maximum operating frequency
450
400
375
333
MHz
Maximum operating current
× 8
590
540
520
480
mA
× 9
590
540
520
480
× 18
600
550
530
490
× 36
760
690
660
600
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1248KV18-450BZXC | 功能描述:靜態(tài)隨機存取存儲器 36MB (2Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12501KV | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C12501KV18-400BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mb x 36 400 MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12501KV18-400BZXC | 功能描述:靜態(tài)隨機存取存儲器 1Mb x 36 400 MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C12501KV18-450BZXC | 功能描述:IC SRAM 36MBIT 450MHZ 165-FPBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
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