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參數(shù)資料
| 型號(hào)： | CY7C1336 |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| 中文描述： | 64K的× 32同步流動(dòng)，通過(guò)3.3V的高速緩存內(nèi)存（3.3 64K的× 32同步流通式高速緩沖內(nèi)存） |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | CY7C1336 |
CY7C1336
PRELIMINARY
4
Cycle Description Table
[1, 2, 3]
Cycle Description
ADD
Used
CE
1
H
CE
3
X
CE
2
X
ZZ
ADSP
ADSP
ADV
WE
OE
CLK
DQ
Deselected Cycle,
Power-Down
None
L
X
L
X
X
X
L-H
High-Z
Deselected Cycle,
Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle,
Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle,
Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle,
Power-Down
None
X
X
X
L
H
L
X
X
X
L-H
High-Z
SNOOZE MODE,
Power-Down
None
X
X
X
H
X
X
X
X
X
X
HIGH-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes:
1.
2.
X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active.
3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CY7C1336F-117AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 7.5ns 100-Pin TQFP |
| CY7C1336H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 64KX32 6.5NS 100TQFP - Bulk |
| CY7C1338B-100AC | 功能描述:IC SRAM 4MBIT 100MHZ 100LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類(lèi)型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán) |
| CY7C1338B-100ACT | 制造商:Cypress Semiconductor 功能描述:Cache Mem 4M-Bit 3.3V SRAM 100-Pin TQFP T/R |
| CY7C1338B-100AXC | 制造商: 功能描述: 制造商:undefined 功能描述: |
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