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參數(shù)資料
| 型號(hào)： | CY7C1336 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| 中文描述： | 64K的× 32同步流動(dòng)，通過3.3V的高速緩存內(nèi)存（3.3 64K的× 32同步流通式高速緩沖內(nèi)存） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 189K |
| 代理商： | CY7C1336 |
CY7C1336
PRELIMINARY
8
AC Test Loads and Waveforms
3.0V
GND
90%
10%
90%
10%
≤
3.0 ns
≤
3.0 ns
OUTPUT
R1=317
R2=351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
1336–3
1336–4
OUTPUT
R
L
=50
Z
0
=50
V
L
=1.5V
3.3V
Switching Characteristics
Over the Operating Range
[8]
Parameter
t
CYC
t
CH
t
CL
t
AS
t
AH
t
CDV
t
DOH
t
ADS
t
ADH
t
WES
t
WEH
t
ADVS
t
ADVH
t
DS
t
DH
t
CES
t
CEH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
t
EOV
Notes:
8.
Unless otherwise noted, test conditions assume signal transition time of 3.0 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
OL
/I
and load capacitance. Shown in (a) and (b) of AC test loads.
9.
t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state voltage.
10. At any given voltage and temperature, t
(max) is less than t
CLZ
(min).
11. This parameter is sampled and not 100% tested.
Description
–117
–100
–66
Min.
8.5
3.0
3.0
2.0
0.5
Max.
Min.
10
4.0
4.0
2.0
0.5
Max.
Min.
15
5.0
5.0
2.5
0.5
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-Up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
BW
[3:0]
, GW,BWE Set-Up Before CLK Rise
BW
[3:0]
, GW,BWE Hold After CLK Rise
ADV Set-Up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up Before CLK Rise
Chip Enable Hold After CLK Rise
Clock to High-Z
[9,10,11]
Clock to Low-Z
[9,10,11]
OE HIGH to Output High-Z
[9,11]
OE LOW to Output Low-Z
[9,11]
OE LOW to Output Valid
7.5
8.0
9.0
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.5
0.5
2.0
2.0
3.5
3.5
6.0
0
0
3.5
3.5
5.0
0
0
1.0
3.5
3.5
6.0
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| CY7C1338B-100AXC | 制造商: 功能描述: 制造商:undefined 功能描述: |
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