參數(shù)資料
型號: CY7C1336
廠商: Cypress Semiconductor Corp.
英文描述: 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM)
中文描述: 64K的× 32同步流動,通過3.3V的高速緩存內(nèi)存(3.3 64K的× 32同步流通式高速緩沖內(nèi)存)
文件頁數(shù): 9/12頁
文件大?。?/td> 189K
代理商: CY7C1336
CY7C1336
PRELIMINARY
9
Timing Diagrams
In/Out
A
t
AH
t
AS
= DON’T CARE
= UNDEFINED
WE is the combination of BWE, BW
[3:0]
, and GW to define a write cycle (see Cycle Description Table).
CE is the combination of CE
2
and CE
3
. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X
t
CLZ
t
CHZ
t
DOH
CLK
ADD
WE
CE1
Data
B
C
D
ADSP
ADSC
ADV
CE
OE
Q(A)
Q(B)
Q
(B+1)
Q
(B+2)
Q
(B+3)
Q(B)
D(C)
D
(C+1)
D
(C+2)
D
(C+3)
Q(D)
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVH
t
ADVS
t
CEH
t
CEH
t
CES
t
CES
t
WEH
t
WES
t
CDV
READ/WRITE Timing
Device originally
deselected
ADSP ignored
with CE
1
HIGH
t
EOHZ
相關(guān)PDF資料
PDF描述
CY7C1337 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM)
CY7C1338G-117AXI 4-Mbit (128K x 32) Flow-Through Sync SRAM
CY7C1338G-133BGXI 4-Mbit (128K x 32) Flow-Through Sync SRAM
CY7C1338G-100AXC 4-Mbit (128K x 32) Flow-Through Sync SRAM
CY7C1338G-100AXI 4-Mbit (128K x 32) Flow-Through Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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