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參數(shù)資料
| 型號： | CY7C1336 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| 中文描述： | 64K的× 32同步流動，通過3.3V的高速緩存內(nèi)存（3.3 64K的× 32同步流通式高速緩沖內(nèi)存） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 189K |
| 代理商： | CY7C1336 |
CY7C1336
PRELIMINARY
5
Pin Descriptions
TQFP Pin
Number
85
Name
ADSC
I/O
Input-
Description
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
1
is deasserted HIGH.
A
1
, A
0
Address Inputs, These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
[1:0]
to select one of the 64K address loca-
tions. Sampled at the rising edge of the CLK, if CE
1
,
CE
2
,
and CE
3
are sampled active,
and ADSP or ADSC is active LOW.
84
ADSP
Input-
Synchronous
36, 37
A
[1:0]
Input-
Synchronous
Input-
Synchronous
49
44,
81–82,
99–100,
32–35
96–93
A
[15:2]
BW
[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BW
0
controls DQ
[7:0]
, BW
1
controls DQ
[15:8]
, BW
2
con-
trols DQ
[23:16]
, BW
3
controls DQ
[31:24]
. See Write Cycle Description Table for further
details.
Advance Input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BW
[3:0]
. Global
writes override byte writes.
Clock Input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
2
and CE
3
, to select/deselect the device. CE
1
gates ADSP.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in con-
junction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins.
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low power
standby mode in which all other inputs are ignored, but the data in the memory array
is maintained. Leaving ZZ floating or NC will default the device into an active state.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC, de-
faults to interleaved burst order.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[15:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE in conjunction with the internal control
logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
are placed in a three-state condition. The outputs are automatically three-stated when
a WRITE cycle is detected.
83
ADV
Input-
Synchronous
87
BWE
Input-
Synchronous
Input-
Synchronous
88
GW
89
98
CLK
CE
1
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
97
CE
2
92
CE
3
86
OE
64
ZZ
Input-
Asynchronous
31
MODE
-
29–28,
25–22,
19–18,
13–12,
9–6, 3–2,
79–78,
75–72,
69–68,
63–62,
59–56,
53–52
15, 41, 65,
91
DQ
[31:0]
I/O-
Synchronous
V
DD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| CY7C1338B-100AXC | 制造商: 功能描述: 制造商:undefined 功能描述: |
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