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參數(shù)資料
| 型號(hào)： | CY7C1350-133ACT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 4.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大小： | 187K |
| 代理商： | CY7C1350-133ACT |
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CY7C1350
6
Write Cycle Descriptions[7, 8]
Function
WE
BWS3
BWS2
BWS1
BWS0
Read
1
XXX
X
Write
No bytes written
0111
1
Write Byte 0
(DQ
[7:0] and DP0)
0111
0
Write Byte 1
(DQ
[15:8] and DP1)
0110
1
Write Bytes 1, 0
0110
0
Write Byte 2
(DQ
[23:16] and DP2)
0101
1
Write Bytes 2, 0
0101
0
Write Bytes 2, 1
0100
1
Write Bytes 2, 1, 0
0100
0
Write Byte 3
(DQ
[31:24] and DP3)
0011
1
Write Bytes 3, 0
0011
0
Write Bytes 3, 1
0010
1
Write Bytes 3, 1, 0
0010
0
Write Bytes 3, 2
0001
1
Write Bytes 3, 2, 0
0001
0
Write Bytes 3, 2, 1
0000
1
Write All Bytes
0000
0
Notes:
7.
X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
8.
Write is initiated by the combination of WE and BWSx.Bytes written are determined by BWS[3:0]. Bytes not selected during byte writes remain unaltered. All
I/Os are three stated during byte writes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1350-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350B-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4.2ns 100-Pin TQFP |
| CY7C1350B-133AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1350F-133AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
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