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參數(shù)資料
| 型號(hào)： | CY7C1350-133ACT |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, 4.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 11/13頁(yè) |
| 文件大?。?/td> | 187K |
| 代理商： | CY7C1350-133ACT |
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CY7C1350
7
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... 65°C to +150°C
Ambient Temperature with
Power Applied
.................................................. 55°C to +125°C
Supply Voltage on VDD Relative to GND .........0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State[9]
.....................................0.5V to V
DDQ + 0.5V
DC Input Voltage[9]
..................................0.5V to V
DDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature[10]
VDD/VDDQ
Com’l
0°C to +70°C
3.3V ± 5%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.465
V
VOH
Output HIGH Voltage
VDD = Min., IOH = –4.0 mA
[11]
2.4
V
VOL
Output LOW Voltage
VDD = Min., IOL = 8.0 mA
[11]
0.4
V
VIH
Input HIGH Voltage
2.0
VDD + 0.3V
V
VIL
Input LOW Voltage[9]
0.3
0.8
V
IX
Input Load Current
GND
≤ V
I ≤ VDDQ
5
A
Input Current of
MODE
30
A
IOZ
Output Leakage
Current
GND
≤ V
I ≤ VDDQ, Output Disabled
5
A
ICC
VDD Operating
Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.0-ns cycle, 143 MHz
450
mA
7.5-ns cycle, 133 MHz
400
mA
10.0-ns cycle, 100 MHz
350
mA
12.5-ns cycle, 80 MHz
300
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
7.0-ns cycle, 143 MHz
60
mA
7.5-ns cycle, 133 MHz
50
mA
10.0-ns cycle, 100 MHz
40
mA
12.5-ns cycle, 80 MHz
35
mA
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
All speed grades
5
mA
ISB3
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
7.0-ns cycle, 143 MHz
50
mA
7.5-ns cycle, 133 MHz
40
mA
10.0-ns cycle, 100 MHz
30
mA
12.5-ns cycle, 80 MHz
25
mA
Note:
9.
Minimum voltage equals –2.0V for pulse duration less than 20 ns.
10. TA is the case temperature.
11. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1350-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350B-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 4.2ns 100-Pin TQFP |
| CY7C1350B-133AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1350F-133AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1350F-200AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 128K x 36 2.8ns 100-Pin TQFP |
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