- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298975 > CY7C1522JV18-250BZI (CYPRESS SEMICONDUCTOR CORP) 8M X 8 DDR SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | CY7C1522JV18-250BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 658K |
| 代理商： | CY7C1522JV18-250BZI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
CY7C1522JV18, CY7C1529JV18
CY7C1523JV18, CY7C1524JV18
Document #: 001-44700 Rev. *B
Page 23 of 27
Switching Characteristics
Over the Operating Range [20]
Cypress
Parameter
Consortium
Parameter
Description
300 MHz
250 MHz
Unit
Min
Max
Min
Max
tPOWER
VDD(Typical) to the First Access
11
ms
tCYC
tKHKH
K Clock and C Clock Cycle Time
3.3
8.4
4.0
8.4
ns
tKH
tKHKL
Input Clock (K/K; C/C) HIGH
1.32
–
1.6
–
ns
tKL
tKLKH
Input Clock (K/K; C/C) LOW
1.32
–
1.6
–
ns
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.49
–
1.8
–
ns
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
01.450
1.8
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.5
–
ns
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.4–
0.5–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.35
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
–
0.35
–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.4–
0.5–
ns
tHC
tKHIX
Control Hold after K Clock Rise (LD, R/W)
0.4–
0.5–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.35
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.3
–
0.35
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data Valid
–0.45–
0.45
ns
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
–0.45
–
–0.45
–
ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–0.45–
0.45
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
0.27
0.30
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.27
–
–0.30
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH [22]
1.24
–
1.55
–
ns
tCQHCQH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
[22]
1.24
–
1.55
–
ns
tCHZ
tCHQZ
Clock (C/C) Rise to High-Z (Active to High-Z) [23, 24]
–0.45–
0.45
ns
tCLZ
tCHQX1
Clock (C/C) Rise to Low-Z [23, 24]
–0.45
–
–0.45
–
ns
DLL Timing
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
ns
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
Cycles
tKC Reset
K Static to DLL Reset
30
ns
Notes
21. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
22. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production
23. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.
24. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1524KV18-333BZI | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| CY7C1612KV18-333BZXC | 8M X 18 QDR SRAM, PBGA165 |
| CY7C256-45PC | 32K X 8 OTPROM, 45 ns, PDIP28 |
| CY7C2561KV18-450BZC | 8M X 8 QDR SRAM, 0.37 ns, PBGA165 |
| CY7C2566KV18-450BZI | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1523AV18-200BZC | 功能描述:靜態(tài)隨機存取存儲器 4M x 18 1.8V DDR II SIO 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1523AV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 4M x 18 1.8V DDR II SIO 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1523JV18-300BZXC | 功能描述:靜態(tài)隨機存取存儲器 4Mbx18 72Mb 1.7-1.9V 300 MHz 2 WORD BURST RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1523KV18-250BZ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1523KV18-250BZXC | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 1.8v 250MHz DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。