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參數(shù)資料
| 型號： | CY7C1561KV18-500BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 QDR SRAM, 0.33 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.4 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 827K |
| 代理商： | CY7C1561KV18-500BZI |
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Document Number: 001-15878 Rev. *E
Revised April 03, 2009
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
PRELIMINARY
CY7C1561KV18, CY7C1576KV18
CY7C1563KV18, CY7C1565KV18
Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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Document History Page
Document Title: CY7C1561KV18/CY7C1576KV18/CY7C1563KV18/CY7C1565KV18, 72-Mbit QDR-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Document Number: 001-15878
Rev.
ECN
Submission
Date
Orig. of
Change
Description of Change
**
1120252
See ECN
VKN
New datasheet
*A
1246904
See ECN
VKN/AESA Added 550 and 500 MHz speed bins
Removed 375, 333, and 300 MHz speed bins
Added footnote# 2
*B
1739283
See ECN
VKN/AESA Converted from Advance Information to Preliminary
*C
2065806
See ECN
VKN/AESA Changed PLL lock time from 2048 cycles to 20
μs
Added footnote #22 related to IDD
Corrected typo in the footnote #26
*D
2612383
11/25/2008
VKN/AESA Changed JTAG ID [31:29] from 001 to 000,
Updated Power up sequence waveform and it’s description,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
Updated data sheet template
*E
2683451
04/03/2009
VKN/PYRS Added note on top of the Ordering Information table
Moved to external web
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