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參數(shù)資料
| 型號(hào)： | CYP15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PLENUM VGA VIDEO CABLE 100 FT -MM |
| 中文描述： | 雙通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 18/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYP15G0201DXB |
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CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 18 of 46
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received on
a channel (within the referenced period), the Transition
Detection logic for that channel will assert LFIx. The LFIx
output remains asserted until at least one transition is detected
in each of three adjacent received characters.
Range Controls
The Clock/Data Recovery (CDR) circuit includes logic to
monitor the frequency of the Phase Locked Loop (PLL)
Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
when the incoming data stream resumes after a time in
which it has been “missing”
when the incoming data stream is outside the acceptable
frequency range
To perform this function, the frequency of the VCO is periodi-
cally sampled and compared to the frequency of the REFCLK
[12]
as defined by the reference clock frequency, it is periodi-
cally forced to the correct frequency (as defined by REFCLK,
SPDSEL, and TXRATE) and then released in an attempt to
lock to the input data stream. The sampling and relock period
of the Range Control is calculated as follows: RANGE
CONTROL SAMPLING PERIOD = (REFCLKPERIOD) *
(16000).
During the time that the Range Control forces the PLL VCO to
run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH)
rate, the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLKx) may run at an incorrect rate (depending
on the quality or existence of the input serial data stream).
After a valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)15G0201DXB contains two receive channels that
can be independently enabled and disabled. Each channel
can be enabled or disabled separately through the BOE[3:0]
inputs, as controlled by the RXLE latch-enable signal. When
RXLE is HIGH, the signals present on the BOE[3:0] inputs are
passed through the Receive Channel Enable latch to control
the PLLs and logic of the associated receive channel. The
BOE[3:0] input associated with a specific receive channel is
listed in
Table 9
.
When RXLE = HIGH and BOE[x] = HIGH, the associated
receive channel is enabled to receive and decode a serial
stream. When RXLE = HIGH and BOE[x] = LOW, the
associated receive channel is disabled and internally
configured for minimum power dissipation. If a single channel
of a bonded-pair is disabled, the other receive channels may
not bind correctly. If the disabled channel is selected as the
master channel for insert/delete functions, or recovered clock
select, these functions will not work correctly. Any disabled
channel indicates an asserted LFIx output. When RXLE
returns LOW, the values present on the BOE[3:0] inputs are
latched in the Receive Channel Enable Latch, and remain
there until RXLE returns HIGH to opened the latch again.
[14]
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by high-performance embedded PLLs that track the
frequency of the transitions in the incoming bit streams and
align the phase of their internal bit-rate clocks to the transitions
in the selected serial data streams.
Each CDR accepts a character-rate (bit-rate
÷
10) or
half-character-rate (bit rate
÷
20) reference clock from the
REFCLK input. This REFCLK input is used to
ensure that the VCO (within each CDR) is operating at the
correct frequency (rather than some harmonic of the bit rate)
improve PLL acquisition time
and to limit unlocked frequency excursions of the CDR VCO
when no data is present at the selected Serial Line Receiver.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits set by the range
control monitors, the CDR will switch to track REFCLK instead
of the data stream. Once the CDR output (RXCLKx) frequency
returns back close to REFCLK frequency, the CDR input will
be switched back to the input data stream to check its
frequency. In case no data is present at the input this switching
behavior may result in brief RXCLKx frequency excursions
from REFCLK. However, the validity of the input data stream
is indicated by the LFIx output. The frequency of REFCLK is
required to be within
±
1500 ppm
[12]
of the frequency of the
clock that drives the REFCLK input of the
remote
transmitter
to ensure a lock to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± inputs through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream and frame to the incoming character bound-
aries. If channel bonding is also enabled, a channel alignment
event is also required before the output data may be
considered usable.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream looking for one or more Comma or K28.5 characters at
all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Note:
14. When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be
indeterminate for up to 10 ms.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0201DXB-BBC | ULTRA-THIN SVGA CABLE 10FT MALE/MALE |
| CYP15G0201DXB-BBI | ULTRA-THIN SVGA CABLE 15FT MALE/MALE |
| CYV15G0201DXB | Dual-channel HOTLink II Transceiver |
| CYV15G0201DXB-BBC | Dual-channel HOTLink II Transceiver |
| CYV15G0404RB-BGC | Independent Clock Quad HOTLink Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0201DXB_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYP15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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