參數(shù)資料
型號(hào)： CYP15G0201DXB
廠商： Cypress Semiconductor Corp.
英文描述： PLENUM VGA VIDEO CABLE 100 FT -MM
中文描述： 雙通道HOTLink II收發(fā)器
文件頁(yè)數(shù)： 23/46頁(yè)
文件大?。?/td> 577K
代理商： CYP15G0201DXB
CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 23 of 46
These modes differ in the number bits which are included in
the parity calculation. For all cases, only ODD parity is
provided which ensures that at least one bit of the data bus is
always a logic-1. Those bits covered by parity generation are
listed in
Table 17
.
Parity generation is enabled through the 3-level select
PARCTL input. When PARCTL = LOW, parity checking is
disabled, and the RXOPx outputs are all disabled (High-Z).
When PARCTL = MID (open) and the Decoders are enabled
(DECMODE
≠
LOW), ODD parity is generated for the received
and decoded character in the RXDx[7:0] signals and is
presented on the associated RXOPx output.
When PARCTL = MID (open) and the Decoders are bypassed
(DECMODE = LOW), ODD parity is generated for the received
and decoded character in the RXDx[7:0] and RXSTx[1:0] bit
positions.
When PARCTL = HIGH, ODD parity is generated for the
RXDx[7:0] and the associated RXSTx[2:0] status bits.
Receive Status Bits
When the 10B/8B Decoder is enabled (DECMODE
≠
LOW),
each character presented at the Output Register includes
three associated status bits. These bits are used to identify
if the contents of the data bus are valid
the type of character present
the state of receive BIST operations (regardless of the state
of DECMODE)
character violations
and channel bonding status.
These conditions normally overlap; i.e., a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a Decoder
violation of some specific type. This implies a hierarchy or
priority level to the various status bit combinations. The
hierarchy and value of each status is listed in
Table 18
when
channel bonding enabled and in
Table 19
when channel
bonding is disabled.
Table 17. Output Register Parity Generation
Receive Synchronization State Machine When Channel
Bonding is Enabled
Each receive channel contains a Receive Synchronization
State Machine. This machine handles loss and recovery of bit,
channel, and word framing, and part of the control for channel
bonding. This state machine is enabled whenever the receive
channels are configured for channel bonding (RXMODE[1]
≠
LOW). Separate forms of the state machine exist for the two
different types of status reporting. When operated without
channel bonding (RXMODE[1] = LOW, RX Modes 0 and 1),
these state machines are disabled and characters are
decoded directly. In RX Mode 0 the RESYNC (111b) status is
never reported. In RX Mode 1, neither the RESYNC (111b) or
Channel Lock Detected (010b) status are reported.
Status Type-A Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
COULD_NOT_BOND, and IN_SYNC, as shown in
Figure 2
.
The IN_SYNC state can respond with multiple status types,
while others can respond with only one type.
Status Type-B Receive State Machine
This machine has four primary states: NO_SYNC, RESYNC,
IN_SYNC, and RESYNC_IN_SYNC, as shown in
Figure 3
.
Some of these state can respond with only one status value,
while others can respond with multiple status types.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0]
bits identify the present state of the BIST compare operation.
Within these status decodes, there are three modes of status
reporting. The two normal or data status reporting modes
(Type A and Type B) are selectable through the RXMODE[0]
input. These status types allow compability with legacy
systems, while allowing full reporting in new systems. The third
status mode is used for reporting receive BIST status and
progress. These status values are generated in part by the
Receive Synchronization State Machine, and are listed in
Table 18
. The receive status when the channels are operated
independently with channel bonding disabled is shown in
Table 19
. The receive status when Receive BIST is enabled is
shown in
Table 20
.
Notes:
18. Receive path parity output drivers (RXOPx) are disabled (High-Z) when PARCTL = LOW.
19. When the Decoder is bypassed (DECMODE = LOW) and BIST is not enabled (Receive BIST Latch output is HIGH), RXSTx[2] is driven to a logic-0, except
when the character in the output buffer is a framing character.
Signal
Name
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
Receive Parity Generate Mode (PARCTL)
MID
DECMODE
= LOW
LOW
[18]
HIGH
X
[19]
X
X
X
X
X
X
DECMODE
≠
LOW
X
X
X
X
X
X
X
X
X
X
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
X
X
X
X
X
X
X
X
X
X
X
X
Table 17. Output Register Parity Generation
Signal
Name
Receive Parity Generate Mode (PARCTL)
MID
DECMODE
= LOW
LOW
[18]
HIGH
DECMODE
≠
LOW
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