參數(shù)資料
型號: CYWUSB6935
廠商: Cypress Semiconductor Corp.
英文描述: WirelessUSB LR 2.4-GHz DSSS Radio SoC(WirelessUSB LR 2.4-GHz DSSS無線SoC)
中文描述: 的WirelessUSB LR 2.4 GHz的無線擴頻系統(tǒng)芯片(的WirelessUSB LR 2.4 GHz的無線擴頻芯片)
文件頁數(shù): 18/32頁
文件大?。?/td> 395K
代理商: CYWUSB6935
CYWUSB6935
Document #: 38-16008 Rev. *D
Page 18 of 32
Note:
6.
The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See
Section 4.7
for more details.
Addr: 0x22
REG_RSSI
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
Valid
RSSI
Figure 7-23. Receive Signal Strength Indicator (RSSI)
[6]
Bit
Name
Description
7:6
Reserved
These bits are reserved. This register is read-only.
5
Valid
The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only.
1 = RSSI value is valid
0 = RSSI value is invalid
4:0
RSSI
The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only value
with the higher values indicating stronger received signals meaning more reliable transmissions.
Addr: 0x23
REG_PA
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
PA Bias
Figure 7-24. PA Bias
Bit
Name
Description
7:3
Reserved
These bits are reserved and should be written with zeroes.
2:0
PA Bias
The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or
decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit
power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose
communication a value of 7 is recommended. See
Table 4-1
for typical output power steps based on the PA Bias bit settings.
Addr: 0x24
REG_CRYSTAL_ADJ
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
Clock Output
Disable
Crystal Adjust
Figure 7-25. Crystal Adjust
Bit
7
6
Name
Reserved
Clock Output Disable The Clock Output Disable bit disables the 13-MHz clock driven on the X13OUT pin.
1 = No 13-MHz clock driven
externa
ll
y
0 = 13-MHz
clock
driven
externally
If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels
5+13
n
. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but it
interfere with every 13th channel beginning with 2.405-GHz channel. Therefore, it is recommended that the 13-MHz
clock output pin be disabled when not in use.
Crystal Adjust
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each
increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5 pF,
starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF.
Description
This bit is reserved and should be written with zero.
5:0
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