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參數(shù)資料
| 型號： | CYWUSB6935 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | WirelessUSB LR 2.4-GHz DSSS Radio SoC(WirelessUSB LR 2.4-GHz DSSS無線SoC) |
| 中文描述： | 的WirelessUSB LR 2.4 GHz的無線擴頻系統(tǒng)芯片（的WirelessUSB LR 2.4 GHz的無線擴頻芯片） |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | CYWUSB6935 |
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CYWUSB6935
Document #: 38-16008 Rev. *D
Page 5 of 32
5.2
The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks
the data as shown in
Figure 5-6
. In transmit mode, DIO and
DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in
Figure 5-7
. The application MCU
samples the DIO and DIOVAL on the rising edge of IRQ.
DIO Interface
5.3
The CYWUSB6935 features three sets of interrupts: transmit,
received, and a wake interrupt. These interrupts all share a
single pin (IRQ), but can be independently enabled/disabled.
In transmit mode, all receive interrupts are automatically
disabled, and in receive mode all transmit interrupts are
automatically disabled. However, the contents of the enable
registers are preserved when switching between transmit and
receive modes.
Interrupts are enabled and the status read through 6 registers:
Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt status register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate interrupt status register. It is therefore
possible to use the devices without making use of the IRQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.
The polarity of all interrupts can be set by writing to the Config-
uration register (Reg 0x05), and it is possible to configure the
IRQ pin to be open drain (if active low) or open source (if active
high).
Interrupts
5.3.1
When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake
interrupt indicates that the oscillator has started, and that the
device is ready to receive SPI transfers.
The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pending is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.
Wake Interrupt
5.3.2
Four interrupts are provided to flag the occurrence of transmit
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in
Section 7.0
.
Transmit Interrupts
5.3.3
Eight interrupts are provided to flag the occurrence of receive
events, four each for SERDES A and B. In 64 chips/bit and 32
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enable register (Reg 0x07), and their status
may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine which event caused the IRQ pin to assert.
The function and operation of these interrupts are described in
detail in
Section 7.0
.
Receive Interrupts
Figure 5-6. DIO Receive Sequence
Figure 5-7. DIO Transmit Sequence
DIOVAL
DIO
IRQ
d7
d6
d5
d4
d3
d2
d...
d14
d13
d12
d11
d10
d9
d8
d1
d0
data to mcu
v7
v6
v5
v4
v3
v2
v...
v14
v13
v12
v11
v10
v9
v8
v1
v0
DIOVAL
DIO
IRQ
d7
d6
d5
d4
d3
d2
d...
d14
d13
d12
d11
d10
d9
d8
d1
d0
data from mcu
v7
v6
v5
v4
v3
v2
v...
v14
v13
v12
v11
v10
v9
v8
v1
v0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYWUSB6935_10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:WirelessUSBa?￠ LR 2.4 GHz DSSS Radio SoC |
| CYWUSB6935-28SEI | 功能描述:IC WIRELESS USB 2.4GHZ 28-SOIC RoHS:否 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:WirelessUSB™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤 包裝:管件 |
| CYWUSB6935-48LFI | 功能描述:IC USB WIRELESS 2.4GHZ 48VQFN RoHS:否 類別:RF/IF 和 RFID >> RF 收發(fā)器 系列:WirelessUSB™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:30 系列:- 頻率:4.9GHz ~ 5.9GHz 數(shù)據(jù)傳輸率 - 最大:54Mbps 調(diào)制或協(xié)議:* 應(yīng)用:* 功率 - 輸出:-3dBm 靈敏度:- 電源電壓:2.7 V ~ 3.6 V 電流 - 接收:* 電流 - 傳輸:* 數(shù)據(jù)接口:PCB，表面貼裝 存儲容量:- 天線連接器:PCB，表面貼裝 工作溫度:-25°C ~ 85°C 封裝/外殼:68-TQFN 裸露焊盤 包裝:管件 |
| CYWUSB6935-48LFXC | 功能描述:射頻接收器 Tranciever COM RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| CYWUSB6935-48LFXI | 功能描述:射頻接收器 Tranciever IND RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
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