參數(shù)資料
型號: DAC1008D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 59/98頁
文件大?。?/td> 551K
代理商: DAC1008D650HN
DAC1008D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 December 2010
59 of 98
NXP Semiconductors
DAC1008D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
0
SR_ILA
R/W
soft reset inter-lane alignment
no action
reset
0
1
Table 81.
Default settings are shown highlighted.
Bit
Symbol
FORCE_LOCK register (address 02h) bit description
…continued
Access
Value
Description
Table 82.
Default settings are shown highlighted.
Bit
Symbol
7 to 4
MAN_LOCK_LN1[3:0]
MAN_LOCK_LN_1_0 register (address 03h) bit description
Access
R/W
Value
0h
Description
manual lock setting synchronization word alignment
lane 1
manual lock setting synchronization word alignment
lane 0
3 to 0
MAN_LOCK_LN0[3:0]
R/W
0h
Table 83.
Default settings are shown highlighted.
Bit
Symbol
7 to 4
MAN_LOCK_LN3[3:0]
MAN_LOCK_2_0 register (address 04h) bit description
Access
R/W
Value
0h
Description
manual lock setting synchronization word alignment
lane 3
manual lock setting synchronization word alignment
lane 2
3 to 0
MAN_LOCK_LN2[3:0]
R/W
0h
Table 84.
Bit
7
CA_CNTRL register (address 05h) bit description
Symbol
WORD_SWAP_LN3
Access
R/W
Value
Description
lane 3 bit swapping
dout_ca_ln3[7:0] = din_ca_ln3[7:0]
dout_ca_ln3[7:0] = din_ca_ln3[0:7]
lane 2 bit swapping
dout_ca_ln2[7:0] = din_ca_ln2[7:0]
dout_ca_ln2[7:0] = din_ca_ln2[0:7]
lane 1 bit swapping
dout_ca_ln1[7:0] = din_ca_ln1[7:0]
dout_ca_ln1[7:0] = din_ca_ln1[0:7]
lane 0 bit swapping
dout_ca_ln0[7:0] = din_ca_ln0[7:0]
dout_ca_ln0[7:0] = din_ca_ln0[0:7]
lane 3 sampling mode
din_ca_ln3 sampled at falling edge f10_ln3
din_ca_ln3 sampled at rising edge f10_ln3
lane 2 sampling mode
din_ca_ln2 sampled at falling edge f10_ln2
din_ca_ln2 sampled at rising edge f10_ln2
0
1
6
WORD_SWAP_LN2
R/W
0
1
5
WORD_SWAP_LN1
R/W
0
1
4
WORD_SWAP_LN0
R/W
0
1
3
SELECT_RF_F10_LN3
R/W
0
1
2
SELECT_RF_F10_LN2
R/W
0
1
相關(guān)PDF資料
PDF描述
DAC1008D750HN Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
DAC1008D750HN Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
DAC1208D650HN Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
DAC1208D650HN Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC1008D650HN/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D650HN-C1 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D750 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× interpolating with JESD204A interface
DAC1008D750_11 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating