參數(shù)資料
型號： DAC1008D650HN
廠商： NXP Semiconductors N.V.
元件分類： 外設及接口
英文描述： Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝： DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù)： 86/98頁
文件大小： 551K
代理商： DAC1008D650HN
DAC1008D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 December 2010
86 of 98
NXP Semiconductors
DAC1008D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 182. LN2_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN2_N'[4:0]
Access
R
Value
-
Description
number of bits per sample minus 1
Table 183. LN2_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN2_S[4:0]
Access
R
Value
-
Description
number of samples per converter per frame cycle
minus 1
Table 184. LN2_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Bit
Symbol
7
LN2_HD
4 to 0
LN2_CF[4:0]
Access
R
R
Value
-
-
Description
high density
number of control words per frame cycle
Table 185. LN2_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN2_RES1[7:0]
Access
R
Value
-
Description
lane 2 reserved field
Table 186. LN2_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN2_RES2[7:0]
Access
R
Value
-
Description
lane 2 reserved field
Table 187. LN2_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN2_FCHK[7:0]
Access
R
Value
-
Description
lane 2 checksum
Table 188. LN3_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN3_DID[7:0]
Access
R
Value
-
Description
lane 3 device ID
Table 189. LN3_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Bit
Symbol
3 to 0
LN3_BID[3:0]
Access
R
Value
-
Description
lane 3 bank ID
Table 190. LN3_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN3_LID[4:0]
Access
R
Value
-
Description
lane 3 lane ID
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相關代理商/技術參數(shù)
參數(shù)描述
DAC1008D650HN/C1,5 功能描述:數(shù)模轉換器- DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D650HN-C1 功能描述:數(shù)模轉換器- DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D750 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× interpolating with JESD204A interface
DAC1008D750_11 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
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