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參數(shù)資料
| 型號(hào)： | DAC3550A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | 32-BIT DAC, PQFP44 |
| 封裝： | METRIC, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 5/35頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | DAC3550A |
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DAC 3550A
Micronas
5
2. Functional Description
2.1. I
2
S Interface
The I
2
S interface is the digital audio interface between
the DAC 3550A and external digital audio sources
such as CD/DAT players, MPEG decoders etc. It cov-
ers most of the I
2
S-compatible formats.
All modes have two common features:
1. The MSB is left justified to an I
2
S frame identifica-
tion (WSI) transition.
2. Data is valid on the rising edge of the bit clock CLI.
16-bit mode
In this case, the bit clock is 32
×
fs
audio
. Maximum word
length is 16 bit.
32-bit mode
In this case, the bit clock is 64
×
fs
audio
. Maximum word
length is 32 bit.
Automatic Detection
No I
2
C control is required to switch between 16- and
32-bit mode. It is recommended to switch the
DAC 3550A into mute position during changing
between 16- and 32-bit mode.
For high-quality audio, it is recommended to use the
32-bit mode of the I
2
S interface to make use of the full
dynamic range (if more than 16 bits are available).
Left-Right Selection
Standard I
2
S format defines an audio frame always
starting with left channel and low-state of WSI. How-
ever, I
2
C control allows changing the polarity of WSI.
Delay Bit
Standard I
2
S format requires a delay of one clock
cycle between transitions of WSI and data MSB. In
order to fit other formats, however, this characteristic
can be switched off and on by I
2
C control.
Fig. 2
–
1:
I
2
S 16-bit mode (LR_SEL=0)
Fig. 2
–
2:
I
2
S 32-bit mode (LR_SEL=0)
Note:
Volume mute should be applied before changing
I
2
S mode in order to avoid audible clicks.
CLI
DAI
V
h
V
l
WSI
left 16-bit audio sample
right 16-bit audio sample
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
13 12 11 10
9 8
7
6
5
4
3
2
1
0
15 14
V
h
V
l
V
h
V
l
programmable delay bit
CLI
DAI
V
h
V
l
WSI
left 32-bit audio sample
right 32-bit audio sample
29 28 27 26 25 24
7
6
5
4
3
2
1
0
31 30
V
h
V
l
V
h
V
l
programmable delay bit
29 28 27 26 25 24 7
6
5
4
3
2
1
0
31 30
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