參數(shù)資料
型號(hào)： DAC5573IWR
廠商： Texas Instruments, Inc.
英文描述： QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 19/30頁(yè)
文件大?。?/td> 499K
代理商： DAC5573IWR
www.ti.com
Master Transmitter Writing to a Slave Receiver (DAC5573) in Standard/Fast Modes
All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This
control byte specifies the operation mode of DAC5573 and determines which channel of DAC5573 is being
accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines whether the
following data is power-down data or regular data.
DAC5573
SLAS401–NOVEMBER 2003
With (PD0-Bit = 0) the DAC5573 expects to receive data in the following sequence
HIGH-BYTE –LOW-BYTE –
HIGH-BYTE – LOW-BYTE
..., until a STOP Condition or REPEATED START Condition on the I
2
C bus is
recognized (refer to the DATA INPUT MODE section of Table 4).
With (PD0-Bit = 1) the DAC5573 expects to receive 2 bytes of power-down data (refer to the POWER DOWN
MODE section of Table 4).
Table 4. Write Sequence in F/S Mode
DATA INPUT MODE
Transmitter
Master
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
POWER DOWN MODE
Transmitter
Master
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
DAC5573
Master
MSB
6
5
4
3
2
1
LSB
Comment
Begin sequence
Write addressing (
R/W=0
)
Start
1
0
0
1
1
A1
A0
R/W
DAC5573 Acknowledges
Load 0
DAC5573 Acknowledges
D4
DAC5573 Acknowledges
x
DAC5573 Acknowledges
Data or Stop or Repeated Start
(1)
A3
A2
Load 1
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0=0
)
D7
D6
D5
D3
D2
D1
D0
Writing data word, high byte
x
x
x
x
x
x
x
Writing data word, low byte
Data or done
(2)
MSB
6
5
4
3
2
1
LSB
Comment
Begin sequence
Write addressing
(R/W=0
)
Start
1
0
0
1
1
A1
A0
R/W
DAC5573 Acknowledges
Load 0
DAC5573 Acknowledges
0
DAC5573 Acknowledges
x
DAC5573 Acknowledges
Stop or Repeated Start
(1)
A3
A2
Load 1
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0 = 1
)
PD1
PD2
0
0
0
0
0
Writing data word, high byte
x
x
x
x
x
x
x
Writing data word, low byte
Done
(1)
(2)
Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write.
Once DAC5573 is properly addressed and control byte is sent, HIGH-BYTE-LOW-BYTE sequences can repeat until a STOP condition
or repeated START condition is received.
19
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