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IOV
DD
AND VOLTAGE TRANSLATORS
IOV
DD
pin powers the digital input structures of the DAC5573. For single-supply operation, IOV
DD
can be tied to
V
. For dual-supply operation, the IOV
pin provides interface flexibility with various CMOS logic famil-
ies—connect it to the logic supply of the system. Analog circuits and internal logic of the DAC5573 use V
DD
as
the supply voltage. The external logic high inputs get translated to V
DD
by level shifters. These level shifters use
the IOV
voltage as a reference to shift the incoming logic HIGH levels to V
. IOV
operates from 2.7 V to 5.5
V regardless of the V
DD
voltage, ensuring compatibility with various logic families. Although specified down to 2.7
V, IOV
DD
operates as low as 1.8 V with degraded timing and temperature performance. For lowest power
consumption, ensure that logic V
IH
levels are as close as possible to IOV
DD
, and logic V
IL
levels as close as
possible to GND voltages.
DRIVING RESISTIVE AND CAPACITIVE LOADS
The DAC5573 output stage is capable of driving loads of up to 1000 pF while remaining stable. Within the offset
and gain error margins, the DAC5573 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2
k
can be driven by the DAC5573 while achieving a good load regulation. When the outputs of the DAC are
driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter
into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the
DAC. This only occurs within approximately the top 20 mV of the DAC's digital input-to-voltage output transfer
characteristic. The reference voltage applied to the DAC5573 may be reduced below the supply voltage applied
to V
DD
in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading
conditions).
CROSSTALK
The DAC5573 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low
crosstalk performance. DC crosstalk seen at one channel during a full-scale change on the neighboring channel
is typically less than 0.0025 LSBs. The ac crosstalk measured (for a full-scale, 1-kHz sine wave output generated
at one channel, and measured at the remaining output channel) is typically under –100 dB.
OUTPUT VOLTAGE STABILITY
The DAC5573 exhibits excellent temperature stability of
±
3 ppm/
°
C typical output voltage drift over the specified
temperature range of the device. This enables the output voltage of each channel to stay within a
±
25-μV window
for a
±
1
°
C ambient temperature change. Combined with good dc noise performance and true 8-Bit differential
linearity, the DAC5573 becomes a perfect choice for closed-loop control applications.
SETTLING TIME AND OUTPUT GLITCH PERFORMANCE
Settling time to within the 8-bit accurate range of the DAC5573 is achievable within 6 μs for a full-scale code
change at the input. Worst case settling times between consecutive code changes is typically less than 2 μs. The
high-speed serial interface of the DAC5573 is designed in order to support up to 188-ksps update rate. For
full-scale output swings, the output stage of each DAC5573 channel typically exhibits less than 100 mV of
overshoot and undershoot when driving a 200 pF capacitive load. Code-to-code change glitches are extremely
low (~10 μV) given that the code-to-code transition does not cross an Nx16 code boundary. Due to internal
segmentation of the DAC5573, code-to-code glitches occur at each crossing of an Nx16 code boundary. These
glitches can approach 100 mVs for N = 15, but settle out within ~2 μs.
DAC5573
SLAS401–NOVEMBER 2003
25