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參數(shù)資料
| 型號： | DAC5573IWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 24/30頁 |
| 文件大小： | 499K |
| 代理商： | DAC5573IWR |
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Resistor
String DAC
Powerdown
Circuitry
V
OUT
Amplifier
Resistor
Network
CURRENT CONSUMPTION
The DAC5573 typically consumes 150 μA at V
DD
= 5 V and 125 μA at V
DD
= 3 V for each active channel,
including reference current consumption. Additional current consumption can occur at the digital inputs if V
IH
<<
V
. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA.
DAC5573
SLAS401–NOVEMBER 2003
Table 8. Power-Down Modes of Operation for the DAC5573
CTRL[0]
1
1
1
1
MSB[7]
0
0
1
1
MSB[6]
0
1
0
1
OPERATING MODE
PWD, high impedance DAC output
PWD, 1 k
to GND DAC ouptut
PWD, 100 k
to GND DAC output
PWD, high impedance DAC output
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 μA at 5 V per
channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only
does the supply current fall but also the output stage is also internally switched from the output of the amplifier to
a resistor network of known values. This has the advantage that the output impedance of the device is known
while in power-down mode. There are three different options: The output is connected internally to GND through
a 1 k
resistor, a 100 k
resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 37.
Figure 37. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 μs for V
DD
= 5 V and 5
μs for V
DD
= 3 V. (See the Typical Curves section for additional information.)
The DAC5573 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 8-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR and
DR are both 10 bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR
and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just
like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8])
when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC5573 treats power-down conditions like data
and all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to
all the DAC5573s in the system, or it is possible to simultaneously power down a channel while updating data on
other channels.
24
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|---|---|
| DAC5574 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL TO ANALOG CONVERTER |
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