參數(shù)資料
型號: DAC5573IWR
廠商: Texas Instruments, Inc.
英文描述: QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述: 四,8位,低功耗,電壓輸出,接口數(shù)字,模擬轉(zhuǎn)換器
文件頁數(shù): 21/30頁
文件大?。?/td> 499K
代理商: DAC5573IWR
www.ti.com
DAC5573 as a Slave Transmitter—Standard and Fast Mode
Figure 35 shows the standard and fast mode master receiver addressing a DAC5573
Slave Transmitter
with a
7-bit address.
SLAVE ADDRESS R/W
A Ctrl <7:1>
A
MS-Byte A
LS-Byte
A P
0 (write)
Data Transferred
(2 Bytes + Acknowledge)
PDN-Byte:
PD1
PD2
1
1
1
1
1
1
MSB
LSB
S
PD0
Sr Slave Address
R/W
A
1 (read)
0 = (Normal Mode)
A
PDN-Byte A
LS-Byte
A P
PD0
Sr Slave Address
R/W
A
MS-Byte A
(DAC5573)
(MASTER)
(MASTER)
1 = (Power Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC5573)
(MASTER)
(MASTER)
(MASTER)
PD1 = Power Down Bit
PD2 = Power Down Bit
1 (read)
(DAC5573)
(DAC5573)
DAC5573 as a Slave Transmitter—High-Speed Mode
Figure 36 shows an I
2
C-Master addressing DAC5573 in high-speed mode (with a 7-bit address), as a
Slave
Transmitter
.
Slave Address
R/W A Ctrl <7:1>
A
MS-Byte A
LS-Byte
A P
0 (write)
Data Transferred
(2 Bytes + Acknowledge)
PD0
Sr
Slave Address
R/W
A
1 (read)
0 = (Normal Mode)
A
PDN-Byte A
LS-Byte
A P
PD0
Sr
Slave Address
R/W
A
MS-Byte A
(DAC5573)
(DAC5573)
(DAC5573)
(MASTER)
(MASTER)
1 = (Power Down Flag)
Data Transferred
(3 Bytes + Acknowledge)
(DAC5573)
(MASTER)
(MASTER)
(MASTER)
Sr
HS-Mode
A
S
F/S-Mode
1 (read)
HS-Master Code
DAC5573
SLAS401–NOVEMBER 2003
Figure 35. Standard and Fast Mode: Slave Transmitter
Figure 36. High-Speed Mode: Slave Transmitter
21
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