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參數(shù)資料
| 型號(hào)： | DAC5573IWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 499K |
| 代理商： | DAC5573IWR |
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Master Receiver Reading From a Slave Transmitter (DAC5573) in HS-Mode
When reading data to the DAC5573 in HS-MODE, the master begins to transmit, what is called the
HS-Master
Code
(0000 1XXX) in F/S mode. No device is allowed to acknowledge the
HS-Master Code
, so the
HS-Master
Code
is followed by a NOT acknowledge.
Power-On Reset
The DAC5573 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. Device pins must not be brought high before supply is applied.
Power-Down Modes
The DAC5573 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
corresponds to the mode of operation of the device.
DAC5573
SLAS401–NOVEMBER 2003
The master then
switches
to HS mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC5573 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC5573.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC5573, indicating that it is prepared to transmit data. Two or three bytes of data
are then read back from the DAC5573, depending on the (PD0-Bit). The value of
Buff-Sel1
and
Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC5573 transmits 2 bytes of data,
HIGH-BYTE
followed by
LOW-BYTE
(refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC5573 transmits 3 bytes of data,
POWER-DOWN-BYTE
followed by the
HIGH-BYTE
followed by the
LOW-BYTE
(refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC5573) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter
MSB
Master
Master
0
6
5
4
3
2
1
LSB
Comment
Begin sequence
HS mode master code
No device may acknowledge HS
master code
Start
1
0
0
0
X
X
X
NONE
Not acknowledge
Master
Master
DAC5573
Master
DAC5573
Master
Master
DAC5573
DAC5573
Master
DAC5573
Master
DAC5573
Master
Master
Repeated start
1
DAC5573 acknowledges
Load 0
X
DAC5573 acknowledges
Repeated start
1
1
DAC5573 acknowledges
1
1
Master acknowledges
D4
D3
Master acknowledges
x
x
Master not acknowledges
Stop or repeated start
1
0
0
1
A1
A0
R/W
Write addressing (
R/W=0
)
A3
A2
Load 1
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0 = 1
)
1
0
0
A1
A0
R/W
Read addressing (
R/W=1
)
PD1
PD2
1
1
1
1
Power-down byte
D7
D6
D5
D2
D1
D0
Reading data word, high byte
x
x
x
x
x
x
Reading data word, low byte
Master signal end of read
Done
23
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