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參數(shù)資料
| 型號： | DC570A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2440 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC570A Design File DC570A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.5k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2440 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP |
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LTC2440
24
2440fd
APPLICATIONS INFORMATION
fastest expected input signal. Figure 20 shows the large
signal response of the circuit in Figure 19.
3. Measure noise performance of the complete circuit. A
good technique is to build one amplier for each input,
even if only one will be used in the end application. Bias
both amplier outputs to midscale, with the inputs tied
together. Verify that the noise is as expected, taking into
account the bandwidth of the LTC2440 inputs for the OSR
being used, the amplier’s broadband voltage noise and
1/f corner (if any) and any additional noise due to the
amplier’s current noise and source resistance.
For more information on testing high linearity ADCs, refer
to Linear Technology Design Solutions 11.
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC4 digital lter and
the digital and analog autocalibration circuits determines
the LTC2440 input bandwidth and rejection characteristics.
The digital lter’s response can be adjusted by setting the
oversample ratio (OSR) through the SPI interface or by
supplying an external conversion clock to the fO pin.
Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Amplier
Figure 20. Large Signal Input Settling Time Indicates
Completed Settling with Selected Load Capacitance.
Figure 21. Dynamic Input Current is Attenuated by Load
Capacitance and Completely Settled Before the Next Conversion
Sample Resulting in No Reduction in Performance.
VCC
fO
REF+
REF–
SCK
BUSY
IN+
IN–
SDO
CS
EXT
0.1μF
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
7
5V
10μF
0.01μF
LTC2440
2440 F19
14
10Ω
IN+
5k
C2
C2, C5 TAIYO YUDEN JMK107BJ105MA
4.7μF
8-12V
LT1236-5
1μF
C1
R1
R2
R4
R5
0.01μF
1/2 LTC2051HV
C5
1μF
10Ω
IN–
5k
C4
0.01μF
1/2 LTC2051HV
+
–
+
–
2440 F20
100μs/DIV
100mV/DIV
2440 F21
5ns/DIV
2mV/DIV
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