參數(shù)資料
型號(hào)： DDC118
英文描述： Octal Current Input 20-Bit Analog-To-Digital Converter
中文描述： 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 12/30頁(yè)
文件大?。?/td> 384K
代理商： DDC118
""#
SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
12
DDC118 Frequency Response
The frequency response of the DDC118 is set by the front
end integrators and is that of a traditional continuous time
integrator, as shown in Figure 7. By adjusting T
INT
, the
user can change the 3dB bandwidth and the location of the
notches in the response. The frequency response of the
Σ
converter that follows the front end integrator is of no
consequence because the converter samples a held
signal from the integrators. That is, the input to the
Σ
converter is always a DC signal. Since the output of the
front end integrators are sampled, aliasing can occur.
Whenever the frequency of the input signal exceeds
one-half of the sampling rate, the signal will fold back down
to lower frequencies.
0
10
20
30
40
50
0.1
T
INT
100
T
INT
1
T
INT
10
T
INT
Frequency
G
Figure 7. Frequency Response of the DDC118
Test Mode
When Test Mode is used, the inputs (IN1, IN2, IN3, IN4,
IN5, IN6, IN7, and IN8) are disconnected from the DDC118
integrators to enable the user to measure a zero input
signal regardless of the current supplied to the inputs. In
addition, packets of charge can be transferred to the
integrators in 11pC intervals to measure non-zero values.
The test mode works with both the continuous and
non-continuous modes. The timing diagram for the test
mode is shown in Figure 8 with the timing specifications
given in Table 2.
To enter Test Mode, hold TEST high while CONV
transitions. If TEST is held high during the entire
integration period, the integrators measure a zero value.
This mode can be used to help debug a design or perform
diagnostic tests. To apply packets of charge during Test
Mode, simply strobe TEST low then high before the next
CONV transition. Each rising edge of TEST causes
approximately 11pC of charge to be transferred to the
integrators. This charge transfer is independent of the
integration time. Data retrieval during Test Mode is
identical to normal operation. To exit Test Mode, take
TEST low and allow several cycles after exiting before
using the data.
t
1
t
3
t
4
t
4
t
6
t
5
t
2
Action
CONV
TEST
Integrate B
Integrate A
Test Mode Disabled
0pC into B
11pC into A
22pC into B
33pC into A
Test Mode Disabled
Test Mode Enabled: Inputs Disconnected
Integrate B
Integrate A
Figure 8. Timing Diagram of the Test Mode of the DDC118
Table 2. Timing for the DDC118 in the Test Mode
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
t2
t3
Setup Time for Test Mode Enable
100
ns
Setup Time for Test Mode Disable
100
ns
Hold Time for Test Mode Enable
100
ns
t4
From Rising Edge of TEST to the Edge of CONV while Test Mode
Enabled
1
μ
s
t5
t6
Falling Edge to Rising Edge of TEST
1
μ
s
Rising Edge to Falling Edge of TEST
1
μ
s
相關(guān)PDF資料
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DDC118IRTCR Octal Current Input 20-Bit Analog-To-Digital Converter
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DDC118IRTCR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DDC118IRTCRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DDC118IRTCT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Octal Current-Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DDC118IRTCT 制造商:Texas Instruments 功能描述:IC ADC 20BIT OCTAL 48-VQFN
DDC118IRTCT 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC ((NW))
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