參數(shù)資料
型號(hào)： DDC118
英文描述： Octal Current Input 20-Bit Analog-To-Digital Converter
中文描述： 八路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 384K
代理商： DDC118
""#
SBAS325A JUNE 2004 REVISED JUNE 2005
www.ti.com
17
Ncont Mode
Non-continuous mode of operation is intended for Ranges
1 to 7. It is not recommended to use Range 0 when
operating in non-continuous mode. Figure 13 illustrates
operation in the ncont mode. The integrations come in
pairs (that is, sides A/B or sides B/A) followed by a time
during which no integrations occur. During that time, the
previous integrations are being measured, reset and
auto-zeroed. Before the DDC118 can advance to states 3
or 6, both sides A and B must be finished with the m/r/az
cycle which takes time t
10
. When the m/r/az cycles are
completed, time t
11
is needed to prepare the next side for
integration. This time is required for the ncont mode
because the m/r/az cycle of the ncont mode is slightly
different from that of the cont mode. After the first
integration ends, DVALID goes low in time t
8
. This time is
the same as in the cont mode. The second data will be
ready in time t
9
after the first data is ready. One result of the
naming convention used in this data sheet is that when the
DDC118 is operating in the
ncont mode
, it passes through
both
ncont mode states
and
cont mode states
. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4,
1, 2, 3, 4 ... where 3 and 4 are cont mode states.
Ncont
mode
, by definition, means that for some portion of the
time, neither side A nor B is integrating. States that perform
an integration are labeled
cont mode states
, while those
that do not are called
ncont mode states
. Since
integrations are performed in the ncont mode, just not
continuously, some cont mode states must be used in a
ncont mode state pattern.
SYMBOL
t8
t9
t10
t11
DESCRIPTION
1st ncont Mode Data Ready
2nd ncont Mode Data Ready
ncont Mode m/r/az Cycle
Prepare Side for Integration
VALUE (CLK = 4MHz, CLK_4X = 0)
344.75
±
0.25
μ
s
362.5
μ
s
725.25
±
0.25
μ
s
≥
18
μ
s
VALUE (CLK = 4.8MHz, CLK_4X = 0)
287.292
±
0.208
μ
s
302.083
μ
s
604.375
±
0.208
μ
s
≥
15
μ
s
Figure 13. Non-Continuous Mode Timing
2
3
1
3
4
4
1
2
Int B
Int A
Int B
Int A
m/r/az B
m/r/az A
m/r/az A
m/r/az B
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
10
t
9
t
11
t
8
Side A
Data
Side B
Data
Side A
Data
Side B
Data
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